MikePopoloski / slangLinks
SystemVerilog compiler and language services
☆770Updated this week
Alternatives and similar repositories for slang
Users that are interested in slang are comparing it to the libraries listed below
Sorting:
- Test suite designed to check compliance with the SystemVerilog standard.☆328Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆395Updated this week
- SystemVerilog to Verilog conversion☆639Updated last month
- Common SystemVerilog components☆627Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆581Updated last week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆443Updated 3 months ago
- lowRISC Style Guides☆436Updated last week
- A Linux-capable RISC-V multicore for and by the world☆709Updated last month
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,567Updated 2 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆504Updated 4 months ago
- The UVM written in Python☆434Updated 2 months ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆457Updated this week
- An abstraction library for interfacing EDA tools☆696Updated this week
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆625Updated 2 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,308Updated this week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆721Updated last year
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆533Updated last year
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆298Updated this week
- 32-bit Superscalar RISC-V CPU☆1,036Updated 3 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆559Updated 3 weeks ago
- Bus bridges and other odds and ends☆568Updated 2 months ago
- RISC-V Formal Verification Framework☆602Updated 3 years ago
- Random instruction generator for RISC-V processor verification☆1,135Updated 2 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,080Updated 3 weeks ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆778Updated last month
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆918Updated 7 months ago
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆580Updated 4 years ago
- An open-source static random access memory (SRAM) compiler.☆911Updated 2 months ago
- VeeR EH1 core☆883Updated 2 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆667Updated 3 weeks ago