SystemVerilog compiler and language services
☆1,072Jun 16, 2026Updated this week
Alternatives and similar repositories for slang
Users that are interested in slang are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆463May 31, 2026Updated 2 weeks ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆475Jun 10, 2026Updated last week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,864Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆379Updated this week
- SystemVerilog frontend for Yosys☆229Jun 11, 2026Updated last week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Python bindings for slang, a library for compiling SystemVerilog☆67Jan 18, 2025Updated last year
- SystemVerilog to Verilog conversion☆736Mar 28, 2026Updated 2 months ago
- SystemVerilog linter☆386Nov 6, 2025Updated 7 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆259Updated this week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆328Jun 30, 2025Updated 11 months ago
- An abstraction library for interfacing EDA tools☆771Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆3,693Updated this week
- SystemVerilog synthesis tool☆234Mar 10, 2025Updated last year
- A SystemVerilog Language Server☆205Nov 30, 2025Updated 6 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SystemVerilog language server☆579Jun 4, 2026Updated 2 weeks ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆521Updated this week
- Yosys Open SYnthesis Suite☆4,531Updated this week
- cocotb: Python-based chip (RTL) verification☆2,407Updated this week
- Circuit IR Compilers and Tools☆2,166Updated this week
- A SystemVerilog language server based on the Slang library.☆253Jun 11, 2026Updated last week
- A hardware compiler based on LLHD and CIRCT☆270Jun 30, 2025Updated 11 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆669May 11, 2026Updated last month
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆238Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- high-performance RTL simulator☆194Jun 19, 2024Updated last year
- magma circuits☆263Oct 19, 2024Updated last year
- The UVM written in Python☆550Updated this week
- Icarus Verilog☆3,502Jun 10, 2026Updated last week
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆717Dec 14, 2025Updated 6 months ago
- A dependency management tool for hardware projects.☆377Updated this week
- Code generation tool for control and status registers☆463May 30, 2026Updated 2 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…☆26Updated this week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆797Jun 15, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Hardware generator debugger☆78Feb 12, 2024Updated 2 years ago
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- A Linux-capable RISC-V multicore for and by the world☆812Jun 5, 2026Updated last week
- XLS: Accelerated HW Synthesis☆1,497Updated this week
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆983Apr 21, 2026Updated last month
- Modular hardware build system☆1,166Updated this week
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆609Jan 3, 2026Updated 5 months ago