MikePopoloski / slangLinks
SystemVerilog compiler and language services
☆755Updated this week
Alternatives and similar repositories for slang
Users that are interested in slang are comparing it to the libraries listed below
Sorting:
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆393Updated this week
- SystemVerilog to Verilog conversion☆630Updated 2 weeks ago
- Test suite designed to check compliance with the SystemVerilog standard.☆324Updated this week
- Common SystemVerilog components☆623Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆575Updated 2 weeks ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆438Updated 2 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆497Updated 3 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,545Updated this week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆297Updated 2 months ago
- RISC-V Formal Verification Framework☆602Updated 3 years ago
- lowRISC Style Guides☆428Updated 8 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,286Updated last week
- The UVM written in Python☆429Updated last month
- Functional verification project for the CORE-V family of RISC-V cores.☆545Updated last week
- An abstraction library for interfacing EDA tools☆690Updated 3 weeks ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆915Updated 6 months ago
- Random instruction generator for RISC-V processor verification☆1,126Updated 3 months ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆455Updated 2 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆701Updated last month
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,077Updated last week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆717Updated 11 months ago
- An open-source static random access memory (SRAM) compiler.☆906Updated 2 months ago
- Bus bridges and other odds and ends☆560Updated last month
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,103Updated this week
- ☆564Updated 3 weeks ago
- SystemRDL 2.0 language compiler front-end☆250Updated 2 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆426Updated 2 weeks ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆429Updated last week
- Contains the code examples from The UVM Primer Book sorted by chapters.☆534Updated 3 years ago
- VeeR EH1 core☆878Updated 2 years ago