Alternatives and similar repositories for slang:

Users that are interested in slang are comparing it to the libraries listed below

• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆381Updated 2 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆306Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆590Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆572Updated 2 weeks ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆426Updated 2 weeks ago
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,465Updated this week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆550Updated this week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆426Updated last week
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆288Updated 5 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆401Updated last month
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆592Updated 2 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆658Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆455Updated last week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,203Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆520Updated 2 weeks ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆594Updated last week
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆515Updated last year
• dalance / svlint
  SystemVerilog linter
  ☆334Updated last month
• lowRISC / style-guides
  lowRISC Style Guides
  ☆388Updated 5 months ago
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆680Updated 8 months ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆663Updated last week
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆245Updated last month
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆491Updated last week
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆559Updated 6 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆898Updated 3 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆209Updated 3 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,010Updated last week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆473Updated 2 months ago
• The-OpenROAD-Project / OpenSTA
  OpenSTA engine
  ☆431Updated last week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆943Updated 3 years ago