MikePopoloski / slangLinks
SystemVerilog compiler and language services
☆800Updated this week
Alternatives and similar repositories for slang
Users that are interested in slang are comparing it to the libraries listed below
Sorting:
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆403Updated this week
- SystemVerilog to Verilog conversion☆653Updated last month
- Test suite designed to check compliance with the SystemVerilog standard.☆336Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆593Updated last week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,601Updated last week
- Common SystemVerilog components☆637Updated last week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆300Updated last month
- lowRISC Style Guides☆445Updated last month
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆463Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆516Updated 5 months ago
- A Linux-capable RISC-V multicore for and by the world☆719Updated 3 months ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆445Updated 5 months ago
- Bus bridges and other odds and ends☆576Updated 3 months ago
- The UVM written in Python☆443Updated 3 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,339Updated last week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆728Updated last year
- RISC-V Formal Verification Framework☆605Updated 3 years ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,128Updated this week
- An abstraction library for interfacing EDA tools☆705Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆572Updated this week
- SystemC Reference Implementation☆585Updated 2 months ago
- Random instruction generator for RISC-V processor verification☆1,144Updated last month
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆628Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,098Updated 2 months ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆925Updated 8 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆436Updated 2 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆224Updated last week
- An open-source static random access memory (SRAM) compiler.☆928Updated last month
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆541Updated last year
- Instruction Set Generator initially contributed by Futurewei☆290Updated last year