cambridgehackers / connectalLinks
Connectal is a framework for software-driven hardware development.
☆176Updated 2 years ago
Alternatives and similar repositories for connectal
Users that are interested in connectal are comparing it to the libraries listed below
Sorting:
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆104Updated 7 years ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆133Updated 4 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆173Updated 5 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- OmniXtend cache coherence protocol☆82Updated 5 months ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- ☆88Updated 2 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 9 months ago
- Python-based hardware modeling framework☆244Updated 6 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆125Updated 6 months ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- RISC-V Virtual Prototype☆179Updated 11 months ago
- PCIe library for the Xilinx 7 series FPGAs in the Bluespec language☆83Updated 3 years ago
- Verilog Content Addressable Memory Module☆114Updated 3 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆149Updated 2 weeks ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆218Updated 5 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 6 months ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆126Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆164Updated 5 years ago
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆90Updated 8 months ago
- Chisel components for FPGA projects☆127Updated 2 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- The Task Parallel System Composer (TaPaSCo)☆111Updated 6 months ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆166Updated last month
- Open-source FPGA research and prototyping framework.☆209Updated last year
- Build Customized FPGA Implementations for Vivado☆342Updated this week
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago