RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
☆184May 8, 2025Updated 9 months ago
Alternatives and similar repositories for Toooba
Users that are interested in Toooba are comparing it to the libraries listed below
Sorting:
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆333Jan 23, 2022Updated 4 years ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆376Oct 19, 2023Updated 2 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆170Jul 3, 2020Updated 5 years ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,152Feb 21, 2026Updated last week
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- Bluespec Compiler (BSC)☆1,081Feb 16, 2026Updated 2 weeks ago
- BSC Development Workstation (BDW)☆32Feb 16, 2026Updated 2 weeks ago
- A simple superscalar out-of-order RISC-V microprocessor☆239Feb 24, 2025Updated last year
- ☆309Jan 23, 2026Updated last month
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆226Aug 25, 2020Updated 5 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated last year
- Main page☆129Feb 12, 2020Updated 6 years ago
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆372Jul 12, 2017Updated 8 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆38Feb 16, 2026Updated 2 weeks ago
- ☆258Dec 22, 2022Updated 3 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,828Feb 25, 2026Updated last week
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 3 years ago
- VeeR EL2 Core☆318Feb 23, 2026Updated last week
- RISC-V Formal Verification Framework☆624Apr 6, 2022Updated 3 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,083Feb 5, 2026Updated last month
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last week
- ☆22Nov 3, 2025Updated 4 months ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- A Linux-capable RISC-V multicore for and by the world☆769Feb 9, 2026Updated 3 weeks ago
- The OpenPiton Platform☆772Feb 25, 2026Updated last week
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Apr 7, 2025Updated 10 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,190May 26, 2025Updated 9 months ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- A hand-written recursive decent Verilog parser.☆10Jan 30, 2026Updated last month
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆101Jun 24, 2025Updated 8 months ago
- RISC-V Zve32x Vector Coprocessor☆207Jan 22, 2026Updated last month
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆34Updated this week
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Nov 20, 2024Updated last year
- 32-bit Superscalar RISC-V CPU☆1,179Sep 18, 2021Updated 4 years ago
- VeeR EH1 core☆929May 29, 2023Updated 2 years ago