Alternatives and similar repositories for Toooba

Users that are interested in Toooba are comparing it to the libraries listed below

• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆158Updated 4 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 7 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆196Updated 11 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆237Updated 7 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆153Updated 3 years ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆261Updated this week
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated 2 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆141Updated last week
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆178Updated 6 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆179Updated last year
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆114Updated 3 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆66Updated last year
• chipsalliance / Cores-VeeR-EH2
  ☆238Updated 2 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 7 months ago
• chipsalliance / VeeR-ISS
  ☆137Updated last year
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆112Updated this week
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆74Updated 6 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆286Updated 2 weeks ago
• SpinalHDL / NaxRiscv
  ☆289Updated 3 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆146Updated 7 months ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆95Updated last month
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• riscv / riscv-CMOs
  ☆86Updated 3 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated last month
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆83Updated 4 years ago
• ucb-bar / sha3
  ☆81Updated last year