Alternatives and similar repositories for llhd

Users that are interested in llhd are comparing it to the libraries listed below

• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆261Updated 2 weeks ago
• calyxir / calyx
  Intermediate Language (IL) for Hardware Accelerator Generators
  ☆540Updated this week
• yupferris / kaze
  An HDL embedded in Rust.
  ☆199Updated last year
• fabianschuiki / llhd-sim
  The LLHD reference simulator.
  ☆39Updated 4 years ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆311Updated this week
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆444Updated 4 months ago
• cucapra / filament
  Fearless hardware design
  ☆177Updated last week
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆211Updated last year
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆145Updated last week
• dalance / svlint
  SystemVerilog linter
  ☆352Updated last week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆262Updated 3 weeks ago
• lowRISC / riscv-llvm
  RISC-V support for LLVM projects (LLVM, Clang, ...)
  ☆271Updated 11 months ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆225Updated last year
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆373Updated last year
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆326Updated 3 years ago
• B-Lang-org / bsc
  Bluespec Compiler (BSC)
  ☆1,028Updated last week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 7 months ago
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆227Updated last week
• rdaly525 / coreir
  ☆103Updated 3 years ago
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆603Updated 3 years ago
• phanrahan / magma
  magma circuits
  ☆261Updated 8 months ago
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆238Updated last month
• riscv / sail-riscv
  Sail RISC-V model
  ☆573Updated last week
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆43Updated last year
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆461Updated last week
• VHDL-LS / rust_hdl
  ☆412Updated last week
• vmware-archive / cascade
  A Just-In-Time Compiler for Verilog from VMware Research
  ☆445Updated 4 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 2 months ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆394Updated 6 months ago