Alternatives and similar repositories for llhd

Users that are interested in llhd are comparing it to the libraries listed below

• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆264Updated 6 months ago
• calyxir / calyx
  Intermediate Language (IL) for Hardware Accelerator Generators
  ☆572Updated 2 weeks ago
• yupferris / kaze
  An HDL embedded in Rust.
  ☆202Updated 2 years ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆338Updated this week
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆457Updated 2 months ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆216Updated last year
• fabianschuiki / llhd-sim
  The LLHD reference simulator.
  ☆39Updated 5 years ago
• cucapra / filament
  Fearless hardware design
  ☆185Updated 4 months ago
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆147Updated 2 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆276Updated 3 months ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆374Updated 2 years ago
• dalance / svlint
  SystemVerilog linter
  ☆372Updated 2 months ago
• B-Lang-org / bsc
  Bluespec Compiler (BSC)
  ☆1,070Updated last week
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆230Updated this week
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆329Updated 3 years ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆228Updated 2 years ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆417Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆237Updated last year
• pulp-platform / mempool
  A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
  ☆313Updated 3 weeks ago
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆243Updated 7 months ago
• BSVLang / Main
  Main page
  ☆129Updated 5 years ago
• phanrahan / magma
  magma circuits
  ☆264Updated last year
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆166Updated 3 weeks ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆181Updated 7 months ago
• vmware-archive / cascade
  A Just-In-Time Compiler for Verilog from VMware Research
  ☆449Updated 4 years ago
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆44Updated last year
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆152Updated last month
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆250Updated last year
• lowRISC / riscv-llvm
  RISC-V support for LLVM projects (LLVM, Clang, ...)
  ☆273Updated last year