fabianschuiki / llhd
Low Level Hardware Description — A foundation for building hardware design tools.
☆411Updated 2 years ago
Alternatives and similar repositories for llhd:
Users that are interested in llhd are comparing it to the libraries listed below
- A hardware compiler based on LLHD and CIRCT☆256Updated last year
- An HDL embedded in Rust.☆197Updated last year
- A dependency management tool for hardware projects.☆292Updated this week
- Fearless hardware design☆175Updated last week
- Intermediate Language (IL) for Hardware Accelerator Generators☆527Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆433Updated last month
- The LLHD reference simulator.☆37Updated 4 years ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆235Updated last month
- Time-sensitive affine types for predictable hardware generation☆142Updated 8 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆224Updated 4 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆223Updated last year
- Sail RISC-V model☆524Updated last week
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆366Updated last year
- Working draft of the proposed RISC-V Bitmanipulation extension☆210Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆229Updated 5 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆250Updated last month
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆322Updated 3 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆217Updated 2 weeks ago
- SystemVerilog linter☆340Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆474Updated 2 months ago
- FOSS Flow For FPGA☆383Updated 3 months ago
- A 32-bit RISC-V soft processor☆310Updated last month
- ☆317Updated 7 months ago
- magma circuits☆260Updated 5 months ago
- RISC-V Formal Verification Framework☆596Updated 3 years ago
- A core language for rule-based hardware design 🦑☆148Updated 6 months ago
- ☆77Updated 3 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆387Updated 2 weeks ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆220Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆441Updated last week