rsnikhil / Bluespec_BSV_Formal_SemanticsView external linksLinks
Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
☆18Jul 17, 2016Updated 9 years ago
Alternatives and similar repositories for Bluespec_BSV_Formal_Semantics
Users that are interested in Bluespec_BSV_Formal_Semantics are comparing it to the libraries listed below
Sorting:
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Sep 15, 2017Updated 8 years ago
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago
- A generic test bench written in Bluespec☆57Dec 15, 2020Updated 5 years ago
- ☆19Jul 12, 2024Updated last year
- Libre Silicon Compiler☆22Apr 13, 2021Updated 4 years ago
- Vim plugin for Bluespec SystemVerilog (BSV)☆11Nov 8, 2020Updated 5 years ago
- Bluespec SystemVerilog library for use of the IBM Coherent Accelerator-Processor Interface (CAPI)☆11May 25, 2016Updated 9 years ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Dec 15, 2020Updated 5 years ago
- Netlist and Verilog Haskell Package☆18Nov 21, 2010Updated 15 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- The BERI and CHERI processor and hardware platform☆50Mar 27, 2017Updated 8 years ago
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆13Jan 4, 2021Updated 5 years ago
- ☆12May 20, 2021Updated 4 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- A tool for the automatic generation of Isabelle/HOL correctness proofs for security protocols.☆18Jun 21, 2015Updated 10 years ago
- Verilog development and verification project for HOL4☆28Apr 25, 2025Updated 9 months ago
- A Bluespec SystemVerilog library of miscellaneous components☆18Apr 14, 2025Updated 10 months ago
- Fluid Pipelines☆11May 4, 2018Updated 7 years ago
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 6 years ago
- RISC-V BSV Specification☆23Jan 18, 2020Updated 6 years ago
- Kansas Lava☆50Oct 6, 2019Updated 6 years ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 7 years ago
- A domain-specific language for testing programs using Behavior-Driven Development (BDD) process in Haskell☆19Dec 20, 2014Updated 11 years ago
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 7 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆38Jan 10, 2026Updated last month
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- An executable specification of the RISCV ISA in L3.☆42Mar 1, 2019Updated 6 years ago
- CoreIR Symbolic Analyzer☆74Oct 27, 2020Updated 5 years ago
- Bluespec BSV HLHDL tutorial☆111Mar 29, 2016Updated 9 years ago
- ☆21Aug 1, 2015Updated 10 years ago
- Cross platform Instant Outbidding Bot, Instant Outbidder Bot is designed to outbid all real-time bids within a second by percentage incre…☆100Jan 17, 2023Updated 3 years ago
- Fast PnR toolchain for CGRA☆18Jul 26, 2024Updated last year
- OpenDesign Flow Database☆17Oct 31, 2018Updated 7 years ago
- The PE for the second generation CGRA (garnet).☆18Apr 25, 2025Updated 9 months ago
- A formal semantics of the RISC-V ISA in Haskell☆173Aug 13, 2023Updated 2 years ago
- general-cores☆21Jul 16, 2025Updated 6 months ago
- ☆19Aug 30, 2020Updated 5 years ago
- Craft 2 top-level repository☆14May 15, 2019Updated 6 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆24Nov 15, 2021Updated 4 years ago