B-Lang-org / bdwLinks
BSC Development Workstation (BDW)
☆30Updated 9 months ago
Alternatives and similar repositories for bdw
Users that are interested in bdw are comparing it to the libraries listed below
Sorting:
- A place to share libraries and utilities that don't belong in the core bsc repo☆36Updated 5 months ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated 3 months ago
- ☆56Updated 3 years ago
- OmniXtend cache coherence protocol☆82Updated 2 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆65Updated 9 months ago
- Useful utilities for BAR projects☆32Updated last year
- FPGA tool performance profiling☆102Updated last year
- A time-predictable processor for mixed-criticality systems☆59Updated 9 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- Mutation Cover with Yosys (MCY)☆85Updated 2 weeks ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- ☆49Updated 4 months ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- The specification for the FIRRTL language☆63Updated last week
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Intel Compiler for SystemC☆24Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆20Updated 3 years ago
- ☆12Updated 4 years ago
- Equivalence checking with Yosys☆45Updated 2 weeks ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆18Updated 3 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated last week
- Naive Educational RISC V processor☆87Updated last month