B-Lang-org / bdw
BSC Development Workstation (BDW)
☆28Updated 5 months ago
Alternatives and similar repositories for bdw:
Users that are interested in bdw are comparing it to the libraries listed below
- A place to share libraries and utilities that don't belong in the core bsc repo☆35Updated last month
- ☆55Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- A SystemVerilog source file pickler.☆56Updated 6 months ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- ☆35Updated 2 weeks ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Determines the modules declared and instantiated in a SystemVerilog file☆44Updated 6 months ago
- ☆36Updated 2 years ago
- An automatic clock gating utility☆46Updated this week
- Equivalence checking with Yosys☆42Updated last week
- Intel Compiler for SystemC☆23Updated last year
- ☆23Updated 4 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆40Updated 2 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- An implementation of RISC-V☆30Updated 2 weeks ago
- A fault-injection framework using Chisel and FIRRTL☆35Updated 2 years ago
- Library of open source Process Design Kits (PDKs)☆37Updated this week
- ☆27Updated 2 months ago
- The multi-core cluster of a PULP system.☆89Updated 2 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 7 months ago
- ☆30Updated 4 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆17Updated 10 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago