B-Lang-org / bdwLinks
BSC Development Workstation (BDW)
☆30Updated 9 months ago
Alternatives and similar repositories for bdw
Users that are interested in bdw are comparing it to the libraries listed below
Sorting:
- A place to share libraries and utilities that don't belong in the core bsc repo☆36Updated 4 months ago
- ☆56Updated 3 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- A time-predictable processor for mixed-criticality systems☆59Updated 8 months ago
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Mutation Cover with Yosys (MCY)☆85Updated 3 weeks ago
- OmniXtend cache coherence protocol☆82Updated last month
- FPGA tool performance profiling☆102Updated last year
- The specification for the FIRRTL language☆59Updated last week
- Chisel Cheatsheet☆33Updated 2 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated 2 months ago
- Useful utilities for BAR projects☆32Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆178Updated 2 months ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- Equivalence checking with Yosys☆45Updated 3 weeks ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆109Updated 2 months ago
- YosysHQ SVA AXI Properties☆41Updated 2 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- Naive Educational RISC V processor☆85Updated 2 weeks ago
- Intel Compiler for SystemC☆24Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆20Updated 3 years ago