Alternatives and similar repositories for xls:

Users that are interested in xls are comparing it to the libraries listed below

• llvm / circt
  Circuit IR Compilers and Tools
  ☆1,778Updated this week
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆967Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,255Updated 2 weeks ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,068Updated last week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆677Updated 3 weeks ago
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆383Updated 5 months ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆671Updated last week
• B-Lang-org / bsc
  Bluespec Compiler (BSC)
  ☆991Updated 3 weeks ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆885Updated this week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,507Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆610Updated 2 weeks ago
• sylefeb / Silice
  Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…
  ☆1,352Updated last week
• vortexgpgpu / vortex
  ☆1,454Updated 2 weeks ago
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆3,728Updated this week
• hughperkins / VeriGPU
  OpenSource GPU, in Verilog, loosely based on RISC-V ISA
  ☆962Updated 4 months ago
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,501Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,516Updated 2 weeks ago
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,411Updated last week
• The-OpenROAD-Project / OpenLane
  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…
  ☆1,447Updated last month
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆915Updated last week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆669Updated last month
• calyxir / calyx
  Intermediate Language (IL) for Hardware Accelerator Generators
  ☆520Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,084Updated last month
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,800Updated this week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆865Updated last year
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆562Updated last week
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆407Updated 3 weeks ago
• KastnerRG / pp4fpgas
  Parallel Programming for FPGAs -- An open-source high-level synthesis book
  ☆812Updated 2 months ago
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆642Updated this week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆1,930Updated last week