Alternatives and similar repositories for xls

Users that are interested in xls are comparing it to the libraries listed below

• llvm / circt
  Circuit IR Compilers and Tools
  ☆1,967Updated this week
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,108Updated this week
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆978Updated 5 months ago
• B-Lang-org / bsc
  Bluespec Compiler (BSC)
  ☆1,061Updated 2 weeks ago
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,128Updated last month
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,695Updated 3 months ago
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆402Updated 2 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆748Updated 3 weeks ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆746Updated 2 months ago
• calyxir / calyx
  Intermediate Language (IL) for Hardware Accelerator Generators
  ☆564Updated this week
• google / CFU-Playground
  Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrol…
  ☆536Updated 8 months ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆2,019Updated 6 months ago
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,561Updated this week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,052Updated this week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆724Updated 2 weeks ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆966Updated last month
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,701Updated last month
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆748Updated last year
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆622Updated 2 weeks ago
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,697Updated this week
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,174Updated this week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆878Updated last week
• vortexgpgpu / vortex
  ☆1,794Updated last week
• hughperkins / VeriGPU
  OpenSource GPU, in Verilog, loosely based on RISC-V ISA
  ☆1,129Updated last year
• riscvarchive / riscv-v-spec
  Working draft of the proposed RISC-V V vector extension
  ☆1,053Updated last year
• fabianschuiki / llhd
  Low Level Hardware Description — A foundation for building hardware design tools.
  ☆422Updated 3 years ago
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆886Updated last week
• shioyadan / Konata
  Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…
  ☆499Updated last year
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,367Updated this week
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆836Updated 5 months ago