Alternatives and similar repositories for bluecheck:

Users that are interested in bluecheck are comparing it to the libraries listed below

• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 7 years ago
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆103Updated 9 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated last week
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆47Updated 2 years ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆100Updated 5 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆80Updated 2 weeks ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆103Updated 5 months ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆71Updated 7 months ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆35Updated last month
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• CakeML / hardware
  Verilog development and verification project for HOL4
  ☆26Updated 5 months ago
• rdaly525 / coreir
  ☆102Updated 2 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆173Updated 8 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆71Updated 4 years ago
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆148Updated 6 months ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆75Updated 9 months ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆20Updated 5 years ago
• CTSRD-CHERI / axe
  Consistency checker for memory subsystem traces
  ☆17Updated 8 years ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆82Updated last year
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆131Updated last week
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated 2 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆91Updated this week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆148Updated 5 months ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆119Updated 10 years ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆49Updated 5 months ago