Alternatives and similar repositories for bluecheck

Users that are interested in bluecheck are comparing it to the libraries listed below

• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 7 years ago
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated this week
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆152Updated 7 months ago
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆48Updated 2 years ago
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆104Updated 9 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆77Updated 10 months ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆72Updated 8 months ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆35Updated last month
• mit-plv / kami
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆153Updated 7 months ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• riscvarchive / ISA_Formal_Spec_Public_Review
  Locus site for Public Review of Several RISC-V ISA Formal Specs
  ☆73Updated 4 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆80Updated last week
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆103Updated 6 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆72Updated 4 years ago
• rdaly525 / coreir
  ☆102Updated 2 years ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated 3 weeks ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆137Updated last week
• CTSRD-CHERI / axe
  Consistency checker for memory subsystem traces
  ☆19Updated 8 years ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• sifferman / schematics
  Examples of how to Generate Schematics from SystemVerilog Synthesis Tools
  ☆22Updated last year
• ymherklotz / vericert
  A formally verified high-level synthesis tool based on CompCert and written in Coq.
  ☆92Updated 10 months ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆58Updated 6 months ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆37Updated last month
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆194Updated 10 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆103Updated this week
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆82Updated last year