Alternatives and similar repositories for blarney:

Users that are interested in blarney are comparing it to the libraries listed below

• rsnikhil / Forvis_RISCV-ISA-Spec
  Formal specification of RISC-V Instruction Set
  ☆98Updated 4 years ago
• adamwalker / clash-riscv
  A RiscV processor implementing the RV32I instruction set written in Clash
  ☆52Updated 6 years ago
• GaloisInc / grift
  Galois RISC-V ISA Formal Tools
  ☆56Updated last year
• christiaanb / contranomy
  ☆27Updated 3 years ago
• sifive / Kami
  Kami - a DSL for designing Hardware in Coq, and the associated semantics and theorems for proving its correctness. Kami is inspired by Bl…
  ☆199Updated 4 years ago
• bittide / bittide-hardware
  ☆19Updated this week
• mit-plv / riscv-semantics
  A formal semantics of the RISC-V ISA in Haskell
  ☆161Updated last year
• braibant / Synthesis
  ☆21Updated 9 years ago
• gergoerdi / clashilator
  Generate interface between Clash and Verilator
  ☆22Updated 9 months ago
• sifive / RiscvSpecFormal
  The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, mod…
  ☆76Updated 4 years ago
• thoughtpolice / clash-playground
  A Clash playground/starter kit, using Nix
  ☆35Updated 6 years ago
• adamwalker / clash-utils
  A collection of reusable Clash designs/examples
  ☆49Updated last year
• rsnikhil / ICFP2020_Bluespec_Tutorial
  Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
  ☆69Updated 2 years ago
• haflang / heron
  A special-purpose processor for pure, non-strict functional languages
  ☆27Updated last month
• mit-plv / kami
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆146Updated 4 months ago
• CakeML / hardware
  Verilog development and verification project for HOL4
  ☆25Updated 3 months ago
• polygonhell / Clash6502
  On going experiments with Clash
  ☆22Updated 9 years ago
• ku-fpg / kansas-lava
  Kansas Lava
  ☆46Updated 5 years ago
• project-oak / silveroak
  Formal specification and verification of hardware, especially for security and privacy.
  ☆124Updated 2 years ago
• clash-lang / clash-starters
  Projects to get started with Clash
  ☆26Updated last month
• mit-plv / riscv-coq
  RISC-V Specification in Coq
  ☆111Updated 3 weeks ago
• gergoerdi / clash-intel8080
  Intel 8080 CPU core: software emulator and CLaSH hardware description
  ☆25Updated 2 years ago
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆147Updated 4 months ago
• expipiplus1 / clash-wavedrom
  ☆15Updated last year
• POETSII / tinsel
  Manythread RISC-V overlay for FPGA clusters
  ☆35Updated 2 years ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆53Updated last week
• thoughtpolice / rv32-sail
  32-bit RISC-V Emulator
  ☆23Updated 5 years ago
• UlfNorell / x86-agda
  Inline, type safe X86-64 assembly programming in Agda
  ☆67Updated 6 years ago
• mgajda / clash-yosys-demo
  Deploying Haskell to Lattice iCE40 using fully open source toolchain
  ☆13Updated 8 years ago
• standardsemiconductor / VELDT-getting-started
  Where Lions Roam: Haskell & Hardware on VELDT
  ☆21Updated 8 months ago