Alternatives and similar repositories for blarney

Users that are interested in blarney are comparing it to the libraries listed below

• adamwalker / clash-riscv
  A RiscV processor implementing the RV32I instruction set written in Clash
  ☆53Updated 7 years ago
• rsnikhil / Forvis_RISCV-ISA-Spec
  Formal specification of RISC-V Instruction Set
  ☆100Updated 5 years ago
• GaloisInc / grift
  Galois RISC-V ISA Formal Tools
  ☆60Updated 2 months ago
• bittide / bittide-hardware
  ☆22Updated this week
• adamwalker / clash-utils
  A collection of reusable Clash designs/examples
  ☆53Updated last year
• christiaanb / contranomy
  ☆30Updated 4 years ago
• mit-plv / riscv-semantics
  A formal semantics of the RISC-V ISA in Haskell
  ☆170Updated 2 years ago
• braibant / Synthesis
  ☆21Updated 10 years ago
• clash-lang / clash-starters
  Projects to get started with Clash
  ☆30Updated 2 months ago
• gergoerdi / clashilator
  Generate interface between Clash and Verilator
  ☆22Updated last year
• haflang / heron
  A special-purpose processor for pure, non-strict functional languages
  ☆30Updated 9 months ago
• mit-plv / kami
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆162Updated 3 weeks ago
• ku-fpg / kansas-lava
  Kansas Lava
  ☆49Updated 6 years ago
• project-oak / silveroak
  Formal specification and verification of hardware, especially for security and privacy.
  ☆127Updated 3 years ago
• rsnikhil / ICFP2020_Bluespec_Tutorial
  Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
  ☆74Updated 2 years ago
• polygonhell / Clash6502
  On going experiments with Clash
  ☆22Updated 10 years ago
• thoughtpolice / clash-playground
  A Clash playground/starter kit, using Nix
  ☆36Updated 6 years ago
• POETSII / tinsel
  Manythread RISC-V overlay for FPGA clusters
  ☆38Updated last month
• CakeML / hardware
  Verilog development and verification project for HOL4
  ☆27Updated 6 months ago
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆162Updated 2 weeks ago
• thoughtpolice / rv32-sail
  32-bit RISC-V Emulator
  ☆26Updated 6 years ago
• mit-plv / riscv-coq
  RISC-V Specification in Coq
  ☆116Updated 3 weeks ago
• philzook58 / nand2coq
  Build an educational formally verified version of the Nand 2 Tetris course using Coq (and other formal tools).
  ☆58Updated 3 years ago
• CTSRD-CHERI / bluecheck
  A generic test bench written in Bluespec
  ☆56Updated 4 years ago
• expipiplus1 / clash-wavedrom
  ☆17Updated last year
• clash-lang / clash-protocols
  a battery-included library for dataflow protocols
  ☆22Updated 3 weeks ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated last month
• UlfNorell / x86-agda
  Inline, type safe X86-64 assembly programming in Agda
  ☆70Updated 6 years ago
• gergoerdi / clash-spaceinvaders
  Intel 8080-based Space Invaders arcade machine implemented on an FPGA, written in CLaSH
  ☆48Updated 2 years ago
• Feldspar / feldspar-language
  The goal of the Feldspar project is to define a high-level language that allows description of high-performance digital signal processing…
  ☆47Updated 4 years ago