Alternatives and similar repositories for blarney:

Users that are interested in blarney are comparing it to the libraries listed below

• adamwalker / clash-riscv
  A RiscV processor implementing the RV32I instruction set written in Clash
  ☆53Updated 6 years ago
• GaloisInc / grift
  Galois RISC-V ISA Formal Tools
  ☆56Updated last year
• rsnikhil / Forvis_RISCV-ISA-Spec
  Formal specification of RISC-V Instruction Set
  ☆99Updated 4 years ago
• adamwalker / clash-utils
  A collection of reusable Clash designs/examples
  ☆49Updated last year
• mit-plv / riscv-semantics
  A formal semantics of the RISC-V ISA in Haskell
  ☆161Updated last year
• bittide / bittide-hardware
  ☆19Updated this week
• gergoerdi / clashilator
  Generate interface between Clash and Verilator
  ☆22Updated 10 months ago
• christiaanb / contranomy
  ☆29Updated 4 years ago
• clash-lang / clash-starters
  Projects to get started with Clash
  ☆27Updated 2 months ago
• haflang / heron
  A special-purpose processor for pure, non-strict functional languages
  ☆28Updated 2 months ago
• mit-plv / kami
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆149Updated 5 months ago
• braibant / Synthesis
  ☆21Updated 9 years ago
• rsnikhil / ICFP2020_Bluespec_Tutorial
  Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
  ☆71Updated 2 years ago
• project-oak / silveroak
  Formal specification and verification of hardware, especially for security and privacy.
  ☆124Updated 2 years ago
• ku-fpg / kansas-lava
  Kansas Lava
  ☆46Updated 5 years ago
• CakeML / hardware
  Verilog development and verification project for HOL4
  ☆25Updated 4 months ago
• thoughtpolice / clash-playground
  A Clash playground/starter kit, using Nix
  ☆35Updated 6 years ago
• thoughtpolice / rv32-sail
  32-bit RISC-V Emulator
  ☆23Updated 6 years ago
• vegaluisjose / reticle-evaluation
  Reticle evaluation (PLDI 2021)
  ☆12Updated 3 years ago
• polygonhell / Clash6502
  On going experiments with Clash
  ☆22Updated 9 years ago
• POETSII / tinsel
  Manythread RISC-V overlay for FPGA clusters
  ☆35Updated 2 years ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆57Updated this week
• mit-plv / riscv-coq
  RISC-V Specification in Coq
  ☆111Updated last month
• CTSRD-CHERI / bluecheck
  A generic test bench written in Bluespec
  ☆50Updated 4 years ago
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆147Updated 5 months ago
• UlfNorell / x86-agda
  Inline, type safe X86-64 assembly programming in Agda
  ☆68Updated 6 years ago
• gergoerdi / clash-intel8080
  Intel 8080 CPU core: software emulator and CLaSH hardware description
  ☆25Updated 2 years ago
• philzook58 / nand2coq
  Build an educational formally verified version of the Nand 2 Tetris course using Coq (and other formal tools).
  ☆54Updated 3 years ago
• gergoerdi / clash-spaceinvaders
  Intel 8080-based Space Invaders arcade machine implemented on an FPGA, written in CLaSH
  ☆47Updated 2 years ago
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 7 years ago