BSVLang / MainLinks
Main page
☆129Updated 5 years ago
Alternatives and similar repositories for Main
Users that are interested in Main are comparing it to the libraries listed below
Sorting:
- Bluespec BSV HLHDL tutorial☆111Updated 9 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆184Updated 8 months ago
- RISC-V Formal Verification Framework☆178Updated 2 weeks ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆153Updated 3 weeks ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆119Updated 8 months ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆331Updated 4 years ago
- Open-source FPGA research and prototyping framework.☆211Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆109Updated 4 years ago
- A dynamic verification library for Chisel.☆160Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆276Updated 3 weeks ago
- Lipsi: Probably the Smallest Processor in the World☆89Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆170Updated 5 years ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆173Updated this week
- A place to share libraries and utilities that don't belong in the core bsc repo☆38Updated 3 weeks ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆200Updated this week
- RISC-V Torture Test☆212Updated last year
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- high-performance RTL simulator☆186Updated last year
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 6 years ago
- Provides dot visualizations of chisel/firrtl circuits☆123Updated 2 years ago
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆92Updated 3 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆238Updated last year
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Hardware generator debugger☆77Updated last year
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- ☆104Updated 3 years ago
- FPGA tool performance profiling☆105Updated last year