Alternatives and similar repositories for Main

Users that are interested in Main are comparing it to the libraries listed below

• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆111Updated 9 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆183Updated 8 months ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆153Updated 3 weeks ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆177Updated 2 weeks ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆120Updated 8 months ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆170Updated 5 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆89Updated last year
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆211Updated last year
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆38Updated 3 weeks ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆160Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆239Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆331Updated 4 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆200Updated this week
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆211Updated last year
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last month
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 3 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆226Updated 10 months ago
• bsc-loca / sargantana
  ☆125Updated 5 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆90Updated 2 weeks ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆276Updated 3 weeks ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆91Updated 3 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆192Updated 2 years ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆146Updated last year
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆122Updated this week
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 6 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆123Updated 2 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year