BSVLang / MainLinks
Main page
☆128Updated 5 years ago
Alternatives and similar repositories for Main
Users that are interested in Main are comparing it to the libraries listed below
Sorting:
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 5 months ago
- Bluespec BSV HLHDL tutorial☆110Updated 9 years ago
- RISC-V Formal Verification Framework☆156Updated last week
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆115Updated 5 months ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- RISC-V Torture Test☆200Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆233Updated 11 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆148Updated 2 months ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆325Updated 3 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆164Updated 5 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- A dynamic verification library for Chisel.☆156Updated 11 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- high-performance RTL simulator☆178Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- SystemVerilog synthesis tool☆215Updated 7 months ago
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆84Updated last week
- Provides various testers for chisel users☆99Updated 2 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆184Updated last week
- Code used in☆197Updated 8 years ago
- Lipsi: Probably the Smallest Processor in the World☆88Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆269Updated 3 weeks ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆37Updated 7 months ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- Verilog Configurable Cache☆184Updated last week
- ACT hardware description language and core tools.☆120Updated last week
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆165Updated last week
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- Chisel Learning Journey☆110Updated 2 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆108Updated 5 months ago