llvm / circtLinks
Circuit IR Compilers and Tools
☆1,984Updated this week
Alternatives and similar repositories for circt
Users that are interested in circt are comparing it to the libraries listed below
Sorting:
- XLS: Accelerated HW Synthesis☆1,400Updated this week
- Working draft of the proposed RISC-V V vector extension☆1,060Updated last year
- Verilator open-source SystemVerilog simulator and lint system☆3,261Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,082Updated this week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆983Updated 6 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,040Updated 3 weeks ago
- ☆1,829Updated last week
- Flexible Intermediate Representation for RTL☆749Updated last year
- Modular hardware build system☆1,116Updated this week
- Intermediate Language (IL) for Hardware Accelerator Generators☆571Updated this week
- RISC-V Opcodes☆818Updated 2 weeks ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,139Updated 2 months ago
- Digital Design with Chisel☆889Updated last month
- Sail RISC-V model☆643Updated this week
- Spike, a RISC-V ISA Simulator☆2,969Updated this week
- SystemVerilog compiler and language services☆907Updated this week
- A Linux-capable RISC-V multicore for and by the world☆753Updated last month
- OpenSource GPU, in Verilog, loosely based on RISC-V ISA☆1,158Updated last year
- Bluespec Compiler (BSC)☆1,071Updated last week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,723Updated last week
- Berkeley's Spatial Array Generator☆1,162Updated this week
- The OpenPiton Platform☆751Updated 3 months ago
- ☆1,093Updated 3 weeks ago
- Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…☆503Updated last year
- ☆622Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,712Updated this week
- SystemC Reference Implementation☆631Updated 3 weeks ago
- Working Draft of the RISC-V Debug Specification Standard☆502Updated last week
- Chisel: A Modern Hardware Design Language☆4,517Updated this week
- educational microarchitectures for risc-v isa☆728Updated 3 months ago