Circuit IR Compilers and Tools
☆2,255Oct 9, 2026Updated this week
Alternatives and similar repositories for circt
Users that are interested in circt are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Intermediate Language (IL) for Hardware Accelerator Generators☆615Updated this week
- Flexible Intermediate Representation for RTL☆747Aug 20, 2024Updated 2 years ago
- Chisel: A Modern Hardware Design Language☆4,807Updated this week
- A hardware compiler based on LLHD and CIRCT☆271Jun 30, 2025Updated last year
- XLS: Accelerated HW Synthesis☆1,945Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Low Level Hardware Description — A foundation for building hardware design tools.☆437Apr 20, 2022Updated 4 years ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Mar 2, 2023Updated 3 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆56Jul 17, 2023Updated 3 years ago
- Verilator open-source SystemVerilog simulator and lint system☆4,001Updated this week
- SystemVerilog compiler and language services☆1,157Updated this week
- A retargetable MLIR-based machine learning compiler and runtime toolkit.☆3,966Updated this week
- C/C++ frontend for MLIR. Also features polyhedral optimizations, parallel optimizations, and more!☆627Jun 19, 2025Updated last year
- The Torch-MLIR project aims to provide first class support from the PyTorch ecosystem to the MLIR ecosystem.☆1,932Updated this week
- Yosys Open SYnthesis Suite☆4,793Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,418Updated this week
- 💀💀💀 The former home of clangir incubator, now part of the official llvm-project.☆581Feb 21, 2026Updated 7 months ago
- A scalable High-Level Synthesis framework on MLIR☆304May 15, 2024Updated 2 years ago
- high-performance RTL simulator☆196Aug 4, 2026Updated 2 months ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆234Aug 19, 2024Updated 2 years ago
- Digital Design with Chisel☆940Updated this week
- Rocket Chip Generator☆3,883Sep 13, 2026Updated 3 weeks ago
- Berkeley's Spatial Array Generator☆1,502Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,955Sep 23, 2026Updated 2 weeks ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Vitis HLS LLVM source code and examples☆417Aug 4, 2026Updated 2 months ago
- A close-to-metal Python API for programming AMD Ryzen™ AI NPUs (AI Engines), built on an open-source MLIR-based compiler toolchain.☆700Updated this week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,047Updated this week
- Time-sensitive affine types for predictable hardware generation☆152Jan 5, 2026Updated 9 months ago
- magma circuits☆264Oct 19, 2024Updated last year
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆340Apr 20, 2024Updated 2 years ago
- Bluespec Compiler (BSC)☆1,144Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,257Updated this week
- Build Customized FPGA Implementations for Vivado☆391Oct 2, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆475Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆482Jun 10, 2026Updated 4 months ago
- Representation and Reference Lowering of ONNX Models in MLIR Compiler Infrastructure☆1,060Updated this week
- Scala based HDL☆2,051Updated this week
- An open source high level synthesis (HLS) tool built on top of LLVM☆130Jun 11, 2024Updated 2 years ago
- (System)Verilog to Chisel translator☆123May 20, 2022Updated 4 years ago
- The specification for the FIRRTL language☆67Oct 2, 2026Updated last week