llvm / circtLinks
Circuit IR Compilers and Tools
☆1,899Updated this week
Alternatives and similar repositories for circt
Users that are interested in circt are comparing it to the libraries listed below
Sorting:
- XLS: Accelerated HW Synthesis☆1,347Updated this week
- Working draft of the proposed RISC-V V vector extension☆1,046Updated last year
- Verilator open-source SystemVerilog simulator and lint system☆3,062Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,959Updated last week
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,969Updated 4 months ago
- ☆1,655Updated last week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆962Updated 3 months ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,099Updated 6 months ago
- Spike, a RISC-V ISA Simulator☆2,823Updated last week
- Flexible Intermediate Representation for RTL☆747Updated last year
- ☆1,053Updated 3 months ago
- OpenSource GPU, in Verilog, loosely based on RISC-V ISA☆1,082Updated 9 months ago
- RISC-V Opcodes☆792Updated last week
- Intermediate Language (IL) for Hardware Accelerator Generators☆544Updated this week
- Berkeley's Spatial Array Generator☆1,051Updated 2 weeks ago
- Digital Design with Chisel☆859Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,611Updated this week
- Modular hardware build system☆1,077Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,629Updated 2 weeks ago
- Sail RISC-V model☆607Updated this week
- Bluespec Compiler (BSC)☆1,041Updated 3 weeks ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,628Updated 2 weeks ago
- The OpenPiton Platform☆730Updated this week
- Yosys Open SYnthesis Suite☆4,016Updated this week
- RISC-V Proxy Kernel☆659Updated last month
- A Linux-capable RISC-V multicore for and by the world☆734Updated 3 weeks ago
- educational microarchitectures for risc-v isa☆718Updated 2 weeks ago
- SystemC Reference Implementation☆601Updated 3 months ago
- Scala based HDL☆1,848Updated this week
- Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrol…☆522Updated 5 months ago