Alternatives and similar repositories for circt

Users that are interested in circt are comparing it to the libraries listed below

• riscvarchive / riscv-v-spec
  Working draft of the proposed RISC-V V vector extension
  ☆1,044Updated last year
• google / xls
  XLS: Accelerated HW Synthesis
  ☆1,341Updated this week
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,960Updated 3 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,937Updated last week
• riscv-software-src / riscv-isa-sim
  Spike, a RISC-V ISA Simulator
  ☆2,798Updated 2 weeks ago
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,097Updated 5 months ago
• vortexgpgpu / vortex
  ☆1,629Updated this week
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆3,042Updated this week
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆955Updated 2 months ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆790Updated 2 weeks ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆747Updated last year
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆656Updated 3 weeks ago
• riscv-software-src / riscv-tests
  ☆1,043Updated 2 months ago
• B-Lang-org / bsc
  Bluespec Compiler (BSC)
  ☆1,037Updated this week
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,616Updated 2 weeks ago
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,066Updated this week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆855Updated this week
• hughperkins / VeriGPU
  OpenSource GPU, in Verilog, loosely based on RISC-V ISA
  ☆1,066Updated 9 months ago
• calyxir / calyx
  Intermediate Language (IL) for Hardware Accelerator Generators
  ☆545Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆722Updated last week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,615Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,153Updated 2 months ago
• riscv / sail-riscv
  Sail RISC-V model
  ☆597Updated this week
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆1,023Updated 4 months ago
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,529Updated 3 months ago
• accellera-official / systemc
  SystemC Reference Implementation
  ☆594Updated 2 months ago
• shioyadan / Konata
  Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…
  ☆477Updated last year
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆725Updated this week
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆818Updated this week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆718Updated 5 months ago