fabianschuiki / mooreLinks
A hardware compiler based on LLHD and CIRCT
☆261Updated 2 weeks ago
Alternatives and similar repositories for moore
Users that are interested in moore are comparing it to the libraries listed below
Sorting:
- Low Level Hardware Description — A foundation for building hardware design tools.☆419Updated 3 years ago
- The LLHD reference simulator.☆39Updated 4 years ago
- A dependency management tool for hardware projects.☆311Updated this week
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆74Updated last week
- An HDL embedded in Rust.☆199Updated last year
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆444Updated 4 months ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆227Updated last week
- Verilator Porcelain☆47Updated last year
- ☆103Updated 3 years ago
- Read and write VCD (Value Change Dump) files in Rust☆43Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆262Updated 3 weeks ago
- Main page☆126Updated 5 years ago
- Intermediate Language (IL) for Hardware Accelerator Generators☆540Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 2 months ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆160Updated last month
- Time-sensitive affine types for predictable hardware generation☆145Updated last week
- Working draft of the proposed RISC-V Bitmanipulation extension☆211Updated last year
- SystemVerilog linter☆352Updated last week
- Fearless hardware design☆177Updated last week
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆144Updated last month
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆225Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 7 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆221Updated 3 weeks ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- A SystemVerilog source file pickler.☆59Updated 8 months ago
- high-performance RTL simulator☆168Updated last year
- RISC-V Formal Verification Framework☆142Updated last month
- Logic circuit analysis and optimization☆43Updated last week
- 🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆49Updated last month
- magma circuits☆261Updated 8 months ago