fabianschuiki / mooreView external linksLinks
A hardware compiler based on LLHD and CIRCT
☆265Jun 30, 2025Updated 7 months ago
Alternatives and similar repositories for moore
Users that are interested in moore are comparing it to the libraries listed below
Sorting:
- Low Level Hardware Description — A foundation for building hardware design tools.☆426Apr 20, 2022Updated 3 years ago
- The LLHD reference simulator.☆39Aug 26, 2020Updated 5 years ago
- Circuit IR Compilers and Tools☆2,031Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆463Nov 4, 2025Updated 3 months ago
- An HDL embedded in Rust.☆202Nov 15, 2023Updated 2 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- SystemVerilog compiler and language services☆948Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆442Sep 6, 2025Updated 5 months ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 3 years ago
- An abstraction library for interfacing EDA tools☆750Updated this week
- Intel Compiler for SystemC☆27Jun 1, 2023Updated 2 years ago
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- Intermediate Language (IL) for Hardware Accelerator Generators☆582Updated this week
- magma circuits☆264Oct 19, 2024Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆249Sep 6, 2025Updated 5 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆356Updated this week
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆232Feb 6, 2026Updated last week
- A dependency management tool for hardware projects.☆345Updated this week
- Using e-graphs to synthesize netlists from boolean logic.☆14Jul 26, 2023Updated 2 years ago
- ☆104Jun 27, 2022Updated 3 years ago
- Hardware Description Languages☆1,112Jul 14, 2025Updated 7 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆313Jun 30, 2025Updated 7 months ago
- Bluespec Compiler (BSC)☆1,077Jan 28, 2026Updated 2 weeks ago
- A low-level intermediate representation for hardware description languages☆28Jun 28, 2020Updated 5 years ago
- A Just-In-Time Compiler for Verilog from VMware Research☆446Jul 1, 2021Updated 4 years ago
- Hardware generator debugger☆77Feb 12, 2024Updated 2 years ago
- Yosys Open SYnthesis Suite☆4,272Updated this week
- Veryl: A Modern Hardware Description Language☆882Updated this week
- XLS: Accelerated HW Synthesis☆1,426Updated this week
- A core language for rule-based hardware design 🦑☆171Dec 10, 2025Updated 2 months ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆220Dec 23, 2025Updated last month
- The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming languag…☆468Jan 18, 2026Updated 3 weeks ago
- The PE for the second generation CGRA (garnet).☆18Apr 25, 2025Updated 9 months ago
- Debuggable hardware generator☆71Feb 17, 2023Updated 2 years ago
- Experimental flows using nextpnr for Xilinx devices☆253Oct 11, 2024Updated last year
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆97Jan 29, 2026Updated 2 weeks ago
- Verilog parsing and generator crate.☆21Apr 16, 2020Updated 5 years ago
- ☆14Sep 14, 2020Updated 5 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,385Jan 28, 2026Updated 2 weeks ago