Alternatives and similar repositories for moore

Users that are interested in moore are comparing it to the libraries listed below

• fabianschuiki / llhd
  Low Level Hardware Description — A foundation for building hardware design tools.
  ☆426Updated 3 years ago
• fabianschuiki / llhd-sim
  The LLHD reference simulator.
  ☆39Updated 5 years ago
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆105Updated last week
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆343Updated this week
• djg / verilated-rs
  Verilator Porcelain
  ☆49Updated 2 years ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆44Updated last year
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆461Updated 2 months ago
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆231Updated last week
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆44Updated 5 months ago
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆148Updated 3 weeks ago
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆172Updated this week
• yupferris / kaze
  An HDL embedded in Rust.
  ☆202Updated 2 years ago
• cucapra / filament
  Fearless hardware design
  ☆187Updated 5 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆177Updated last week
• BSVLang / Main
  Main page
  ☆129Updated 5 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆183Updated 8 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆275Updated 3 weeks ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆153Updated 3 weeks ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆216Updated last year
• dalance / svlint
  SystemVerilog linter
  ☆373Updated 2 months ago
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• ucsc-vama / essent
  high-performance RTL simulator
  ☆186Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆127Updated last year
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆120Updated 8 months ago
• phanrahan / magma
  magma circuits
  ☆264Updated last year
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆228Updated 2 years ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆245Updated 4 months ago