RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
☆335Jan 23, 2022Updated 4 years ago
Alternatives and similar repositories for Piccolo
Users that are interested in Piccolo are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆377Oct 19, 2023Updated 2 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆184May 8, 2025Updated 10 months ago
- Bluespec Compiler (BSC)☆1,087Feb 16, 2026Updated last month
- BSC Development Workstation (BDW)☆32Feb 16, 2026Updated last month
- Main page☆130Feb 12, 2020Updated 6 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆170Jul 3, 2020Updated 5 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆38Feb 16, 2026Updated last month
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,804Feb 17, 2026Updated last month
- VeeR EH1 core☆931May 29, 2023Updated 2 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,851Updated this week
- "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)☆19Sep 26, 2024Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,197May 26, 2025Updated 9 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Nov 20, 2024Updated last year
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆970Nov 15, 2024Updated last year
- The OpenPiton Platform☆777Feb 25, 2026Updated 3 weeks ago
- Working Draft of the RISC-V Debug Specification Standard☆507Mar 14, 2026Updated last week
- VeeR EL2 Core☆323Mar 12, 2026Updated last week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,157Feb 21, 2026Updated last month
- SERV - The SErial RISC-V CPU☆1,766Feb 19, 2026Updated last month
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,111Mar 11, 2026Updated 2 weeks ago
- 32-bit Superscalar RISC-V CPU☆1,197Sep 18, 2021Updated 4 years ago
- An introductory guide to Bluespec (BSV)☆67May 4, 2019Updated 6 years ago
- A Bluespec SystemVerilog library of miscellaneous components☆18Apr 14, 2025Updated 11 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,044Jun 27, 2024Updated last year
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆243Mar 4, 2026Updated 2 weeks ago
- RISC-V Formal Verification Framework☆626Apr 6, 2022Updated 3 years ago
- PLEASE MOVE TO PAWSv2☆16Feb 2, 2022Updated 4 years ago
- SystemVerilog to Verilog conversion☆709Nov 24, 2025Updated 4 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,075Feb 11, 2026Updated last month
- A small, light weight, RISC CPU soft core☆1,526Dec 8, 2025Updated 3 months ago
- RISC-V Configuration Validator☆82Mar 28, 2025Updated 11 months ago
- RISC-V Processor Trace Specification☆209Mar 18, 2026Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆281Feb 20, 2026Updated last month
- educational microarchitectures for risc-v isa☆740Sep 1, 2025Updated 6 months ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆406Mar 17, 2026Updated last week
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆10Apr 29, 2024Updated last year
- A Linux-capable RISC-V multicore for and by the world☆784Updated this week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,121Sep 10, 2024Updated last year
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago