bluespec / PiccoloLinks
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
☆326Updated 3 years ago
Alternatives and similar repositories for Piccolo
Users that are interested in Piccolo are comparing it to the libraries listed below
Sorting:
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆374Updated 2 years ago
- RISC-V CPU Core☆389Updated 3 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆233Updated 11 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 5 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆164Updated 5 years ago
- RISC-V Formal Verification Framework☆610Updated 3 years ago
- RISC-V Torture Test☆200Updated last year
- Main page☆128Updated 5 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆328Updated 10 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆269Updated 3 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆244Updated 11 months ago
- A simple RISC-V processor for use in FPGA designs.☆279Updated last year
- Instruction Set Generator initially contributed by Futurewei☆295Updated 2 years ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆214Updated last year
- VeeR EL2 Core☆299Updated 2 weeks ago
- ☆245Updated 2 years ago
- ☆297Updated 3 weeks ago
- ☆349Updated last month
- Small footprint and configurable DRAM core☆444Updated this week
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆306Updated this week
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆159Updated 3 years ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆410Updated 3 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆532Updated last month
- mor1kx - an OpenRISC 1000 processor IP core☆556Updated 2 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆274Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆612Updated 2 weeks ago
- RISC-V microcontroller IP core developed in Verilog☆183Updated last week
- SystemVerilog to Verilog conversion☆670Updated 4 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆444Updated 5 months ago
- A Linux-capable RISC-V multicore for and by the world☆741Updated 2 weeks ago