bluespec / PiccoloLinks
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
☆327Updated 3 years ago
Alternatives and similar repositories for Piccolo
Users that are interested in Piccolo are comparing it to the libraries listed below
Sorting:
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆375Updated last year
- RISC-V CPU Core☆369Updated last month
- RISC-V Torture Test☆197Updated last year
- RISC-V Formal Verification Framework☆607Updated 3 years ago
- Main page☆126Updated 5 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 9 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆160Updated 5 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆179Updated 3 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆263Updated 2 months ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆214Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆244Updated 9 months ago
- A simple RISC-V processor for use in FPGA designs.☆279Updated last year
- VeeR EL2 Core☆294Updated last week
- mor1kx - an OpenRISC 1000 processor IP core☆550Updated this week
- FuseSoC-based SoC for VeeR EH1 and EL2☆323Updated 8 months ago
- ☆242Updated 2 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆266Updated 4 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆155Updated 3 years ago
- Small footprint and configurable DRAM core☆433Updated last month
- ☆293Updated last week
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆413Updated last month
- Instruction Set Generator initially contributed by Futurewei☆292Updated last year
- ☆336Updated 11 months ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆464Updated 2 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆525Updated 2 weeks ago
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆302Updated last week
- RISC-V Formal Verification Framework☆145Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆598Updated last week
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated last week
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆292Updated last week