mit-plv / kami
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
☆142Updated last month
Related projects ⓘ
Alternatives and complementary repositories for kami
- Kami - a DSL for designing Hardware in Coq, and the associated semantics and theorems for proving its correctness. Kami is inspired by Bl…☆197Updated 4 years ago
- A formal semantics of the RISC-V ISA in Haskell☆156Updated last year
- The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, mod…☆75Updated 4 years ago
- A core language for rule-based hardware design 🦑☆140Updated 3 weeks ago
- Formal specification and verification of hardware, especially for security and privacy.☆124Updated 2 years ago
- Verilog development and verification project for HOL4☆24Updated this week
- RISC-V Specification in Coq☆109Updated 3 months ago
- Formal specification of RISC-V Instruction Set☆97Updated 4 years ago
- Galois RISC-V ISA Formal Tools☆56Updated 9 months ago
- The source code to the Voss II Hardware Verification Suite☆53Updated last month
- Pono: A flexible and extensible SMT-based model checker☆80Updated 2 weeks ago
- Locus site for Public Review of Several RISC-V ISA Formal Specs☆73Updated 4 years ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆88Updated 4 months ago
- Time-sensitive affine types for predictable hardware generation☆134Updated 3 months ago
- Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference☆66Updated last year
- Haskell library for hardware description☆98Updated last month
- CHERI-RISC-V model written in Sail☆55Updated last month
- The HW-CBMC and EBMC Model Checkers for Verilog☆60Updated this week
- A Haskell to HDL (Verilog/VHDL) Compiler☆24Updated 9 months ago
- ☆21Updated 9 years ago
- Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model☆71Updated last month
- A Modeling and Verification Platform for SoCs using ILAs☆75Updated 4 months ago
- A generic test bench written in Bluespec☆45Updated 3 years ago
- Kami based processor implementations and specifications☆22Updated 4 years ago
- FPGA synthesis tool powered by program synthesis☆38Updated last month
- CoreIR Symbolic Analyzer☆61Updated 4 years ago
- Build an educational formally verified version of the Nand 2 Tetris course using Coq (and other formal tools).☆54Updated 2 years ago
- An executable specification of the RISCV ISA in L3.☆41Updated 5 years ago
- A Library for Representing Recursive and Impure Programs in Coq☆203Updated last month
- BTOR2 MLIR project☆16Updated 9 months ago