mit-plv / kamiLinks
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
☆155Updated 2 weeks ago
Alternatives and similar repositories for kami
Users that are interested in kami are comparing it to the libraries listed below
Sorting:
- A formal semantics of the RISC-V ISA in Haskell☆167Updated last year
- Formal specification and verification of hardware, especially for security and privacy.☆126Updated 3 years ago
- A core language for rule-based hardware design 🦑☆156Updated last month
- The source code to the Voss II Hardware Verification Suite☆55Updated 2 weeks ago
- RISC-V Specification in Coq☆115Updated 5 months ago
- Verilog development and verification project for HOL4☆26Updated 2 months ago
- Formal specification of RISC-V Instruction Set☆100Updated 5 years ago
- Galois RISC-V ISA Formal Tools☆60Updated 3 months ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆92Updated last year
- Pono: A flexible and extensible SMT-based model checker☆105Updated this week
- Time-sensitive affine types for predictable hardware generation☆145Updated this week
- Locus site for Public Review of Several RISC-V ISA Formal Specs☆73Updated 5 years ago
- A generic test bench written in Bluespec☆53Updated 4 years ago
- Haskell library for hardware description☆104Updated last month
- ☆21Updated 9 years ago
- CoreIR Symbolic Analyzer☆73Updated 4 years ago
- A Modeling and Verification Platform for SoCs using ILAs☆78Updated last year
- CHERI-RISC-V model written in Sail☆60Updated 3 weeks ago
- BTOR2 MLIR project☆26Updated last year
- The HW-CBMC and EBMC Model Checkers for Verilog☆79Updated this week
- Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference☆73Updated 2 years ago
- FPGA synthesis tool powered by program synthesis☆51Updated last week
- Reads a state transition system and performs property checking☆84Updated 4 months ago
- UCLID5: formal modeling, verification, and synthesis of computational systems☆145Updated last week
- IC3 reference implementation: a short, simple, fairly competitive implementation of IC3. Read it, tune it, extend it, play with it.☆59Updated 10 years ago
- ☆40Updated 3 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 7 years ago
- Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model☆80Updated 2 weeks ago
- Manythread RISC-V overlay for FPGA clusters☆38Updated 2 years ago
- Build an educational formally verified version of the Nand 2 Tetris course using Coq (and other formal tools).☆57Updated 3 years ago