Alternatives and similar repositories for Documentation:

Users that are interested in Documentation are comparing it to the libraries listed below

• oxidecomputer / cobalt
  A collection of common Bluespec interfaces/modules.
  ☆98Updated last year
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 2 years ago
• mosscomp / moss
  A computer for human beings.
  ☆44Updated 5 months ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆88Updated 6 months ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆32Updated 3 years ago
• POETSII / tinsel
  Manythread RISC-V overlay for FPGA clusters
  ☆36Updated 2 years ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆154Updated 8 months ago
• cucapra / filament
  Fearless hardware design
  ☆175Updated last week
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆35Updated last month
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆103Updated last month
• camel-cdr / rvv-bench-results
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)
  ☆31Updated last week
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 3 years ago
• CHERIoT-Platform / cheriot-sail
  Sail code model of the CHERIoT ISA
  ☆37Updated last month
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆82Updated last year
• oxidecomputer / tockilator
  Deducing Tock execution flows from Ibex Verilator traces
  ☆70Updated 2 years ago
• B-Lang-org / bdw
  BSC Development Workstation (BDW)
  ☆28Updated 5 months ago
• sifiveinc / wake
  The SiFive wake build tool
  ☆89Updated this week
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆70Updated this week
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆84Updated 5 years ago
• frwang96 / verik
  Verik toolchain
  ☆43Updated 2 years ago
• gatecat / prjoxide
  Documenting Lattice's 28nm FPGA parts
  ☆142Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆174Updated 9 months ago
• f4pga / ideas
  Random ideas and interesting ideas for things we hope to eventually do.
  ☆86Updated 3 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆41Updated 4 months ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆100Updated 5 years ago
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆29Updated last week
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆58Updated 2 weeks ago
• djg / verilated-rs
  Verilator Porcelain
  ☆48Updated last year