Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
☆1,858Jun 9, 2026Updated this week
Alternatives and similar repositories for verible
Users that are interested in verible are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆463May 31, 2026Updated 2 weeks ago
- SystemVerilog compiler and language services☆1,068Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆475Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆378Updated this week
- SystemVerilog language server☆579Jun 4, 2026Updated last week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- SystemVerilog linter☆386Nov 6, 2025Updated 7 months ago
- Verilator open-source SystemVerilog simulator and lint system☆3,679Updated this week
- cocotb: Python-based chip (RTL) verification☆2,407Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆258May 31, 2026Updated 2 weeks ago
- SystemVerilog to Verilog conversion☆736Mar 28, 2026Updated 2 months ago
- A SystemVerilog Language Server☆205Nov 30, 2025Updated 6 months ago
- An abstraction library for interfacing EDA tools☆771Apr 24, 2026Updated last month
- Yosys Open SYnthesis Suite☆4,531Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,593Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- SystemVerilog synthesis tool☆234Mar 10, 2025Updated last year
- Random instruction generator for RISC-V processor verification☆1,313Apr 3, 2026Updated 2 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,420Jun 8, 2026Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆669May 11, 2026Updated last month
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆328Jun 30, 2025Updated 11 months ago
- Icarus Verilog☆3,489Updated this week
- Common SystemVerilog components☆757Jun 5, 2026Updated last week
- Code generation tool for control and status registers☆463May 30, 2026Updated 2 weeks ago
- A dependency management tool for hardware projects.☆375Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- The UVM written in Python☆550Updated this week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆797Jun 15, 2024Updated 2 years ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆715Dec 14, 2025Updated 6 months ago
- Verilog/SystemVerilog Syntax and Omni-completion☆418Oct 13, 2024Updated last year
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,918Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆518Updated this week
- ☆134Nov 17, 2025Updated 6 months ago
- Hardware Description Languages☆1,151Apr 6, 2026Updated 2 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,824Mar 25, 2026Updated 2 months ago
- Chisel: A Modern Hardware Design Language☆4,680Jun 4, 2026Updated last week
- Verilog/SystemVerilog support for VS Code, including syntax highlighting, snippets, formatting, linting, project-aware navigation, hierar…☆372Updated this week
- Open source implementation of a Verilog formatter☆181Jan 27, 2022Updated 4 years ago
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆609Jan 3, 2026Updated 5 months ago
- XLS: Accelerated HW Synthesis☆1,498Updated this week
- lowRISC Style Guides☆512Apr 21, 2026Updated last month