Alternatives and similar repositories for verible:

Users that are interested in verible are comparing it to the libraries listed below

• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆591Updated this week
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆680Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,066Updated 2 weeks ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆595Updated last week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,204Updated 3 weeks ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆1,887Updated this week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,471Updated this week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,010Updated last week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆572Updated 2 weeks ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,240Updated this week
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆708Updated this week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆848Updated last year
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆663Updated last week
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆758Updated 2 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆551Updated this week
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆680Updated 8 months ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆426Updated 2 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆389Updated 5 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆898Updated 3 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆592Updated 2 years ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,054Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆658Updated last week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆943Updated 3 years ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,609Updated last year
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆802Updated 2 weeks ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆871Updated last week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆306Updated this week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆958Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,486Updated 3 weeks ago
• accellera-official / systemc
  SystemC Reference Implementation
  ☆528Updated last week