Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
☆1,959Sep 23, 2026Updated 3 weeks ago
Alternatives and similar repositories for verible
Users that are interested in verible are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆475Updated this week
- SystemVerilog compiler and language services☆1,163Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆482Jun 10, 2026Updated 4 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆399Updated this week
- SystemVerilog language server☆586Sep 14, 2026Updated last month
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- SystemVerilog linter☆393Nov 6, 2025Updated 11 months ago
- Verilator open-source SystemVerilog simulator and lint system☆4,008Updated this week
- cocotb: Python-based chip (RTL) verification☆2,542Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆269Oct 4, 2026Updated last week
- SystemVerilog to Verilog conversion☆755Aug 18, 2026Updated last month
- A SystemVerilog Language Server☆211Nov 30, 2025Updated 10 months ago
- An abstraction library for interfacing EDA tools☆802Sep 15, 2026Updated 3 weeks ago
- Yosys Open SYnthesis Suite☆4,805Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,722Sep 24, 2026Updated 2 weeks ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- SystemVerilog synthesis tool☆237Mar 10, 2025Updated last year
- Random instruction generator for RISC-V processor verification☆1,366Sep 21, 2026Updated 3 weeks ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,476Sep 25, 2026Updated 2 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆691Oct 8, 2026Updated last week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆334Jun 30, 2025Updated last year
- Icarus Verilog☆3,678Updated this week
- Common SystemVerilog components☆808Sep 18, 2026Updated 3 weeks ago
- Code generation tool for control and status registers☆471Sep 11, 2026Updated last month
- A dependency management tool for hardware projects.☆398Oct 1, 2026Updated 2 weeks ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- The UVM written in Python☆572Oct 6, 2026Updated last week
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆741Updated this week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆802Jun 15, 2024Updated 2 years ago
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- Verilog/SystemVerilog Syntax and Omni-completion☆424Aug 3, 2026Updated 2 months ago
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,106Updated this week
- ☆137Nov 17, 2025Updated 10 months ago
- Hardware Description Languages☆1,181Jul 9, 2026Updated 3 months ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆556Sep 19, 2026Updated 3 weeks ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,966Mar 25, 2026Updated 6 months ago
- Chisel: A Modern Hardware Design Language☆4,809Updated this week
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆631Jan 3, 2026Updated 9 months ago
- Verilog/SystemVerilog support for VS Code☆389Updated this week
- Open source implementation of a Verilog formatter☆187Jan 27, 2022Updated 4 years ago
- XLS: Accelerated HW Synthesis☆1,955Updated this week
- lowRISC Style Guides☆545Jul 8, 2026Updated 3 months ago