chipsalliance / verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
☆1,485Updated 3 weeks ago
Alternatives and similar repositories for verible:
Users that are interested in verible are comparing it to the libraries listed below
- SystemVerilog compiler and language services☆695Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,487Updated 2 weeks ago
- SystemVerilog to Verilog conversion☆600Updated 2 weeks ago
- cocotb: Python-based chip (RTL) verification☆1,911Updated this week
- Random instruction generator for RISC-V processor verification☆1,074Updated last month
- VUnit is a unit testing framework for VHDL/SystemVerilog☆763Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,234Updated 2 weeks ago
- Common SystemVerilog components☆583Updated 2 weeks ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆600Updated last month
- Package manager and build abstraction tool for FPGA/ASIC development☆1,250Updated this week
- lowRISC Style Guides☆397Updated 6 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆558Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆428Updated last week
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,061Updated this week
- An abstraction library for interfacing EDA tools☆668Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,023Updated last month
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆723Updated this week
- A Linux-capable RISC-V multicore for and by the world☆666Updated last week
- RISC-V Formal Verification Framework☆596Updated 2 years ago
- Multi-platform nightly builds of open source digital design and verification tools☆978Updated this week
- Hardware Description Languages☆1,006Updated last month
- Digital Design with Chisel☆811Updated last week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆900Updated 3 months ago
- SERV - The SErial RISC-V CPU☆1,502Updated last week
- An open-source static random access memory (SRAM) compiler.☆877Updated 3 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆382Updated last week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,773Updated this week
- The UVM written in Python☆410Updated 2 months ago
- VeeR EH1 core☆858Updated last year
- Functional verification project for the CORE-V family of RISC-V cores.☆503Updated this week