chipsalliance / verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
☆1,321Updated this week
Related projects: ⓘ
- Random instruction generator for RISC-V processor verification☆997Updated 3 weeks ago
- SystemVerilog compiler and language services☆584Updated this week
- cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python☆1,742Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,048Updated last month
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,338Updated this week
- SystemVerilog to Verilog conversion☆535Updated 2 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆926Updated 2 months ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,002Updated this week
- lowRISC Style Guides☆357Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,164Updated this week
- Digital Design with Chisel☆740Updated last month
- RISC-V Formal Verification Framework☆574Updated 2 years ago
- 32-bit Superscalar RISC-V CPU☆840Updated 3 years ago
- VeeR EH1 core☆810Updated last year
- SERV - The SErial RISC-V CPU☆1,375Updated 3 weeks ago
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆615Updated last week
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆536Updated 2 weeks ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆613Updated 3 months ago
- Flexible Intermediate Representation for RTL☆720Updated 3 weeks ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆723Updated this week
- An open-source static random access memory (SRAM) compiler.☆812Updated 2 months ago
- Verilator open-source SystemVerilog simulator and lint system☆2,448Updated this week
- A Linux-capable RISC-V multicore for and by the world☆597Updated 2 weeks ago
- Common SystemVerilog components☆494Updated this week
- An Open-source FPGA IP Generator☆816Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆838Updated 4 months ago
- Verilog AXI components for FPGA implementation☆1,440Updated 9 months ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆394Updated 9 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,572Updated this week
- A small, light weight, RISC CPU soft core☆1,268Updated 3 weeks ago