Alternatives and similar repositories for Flute

Users that are interested in Flute are comparing it to the libraries listed below

• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆327Updated 3 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆387Updated 3 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 10 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆610Updated 3 years ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆215Updated last year
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆245Updated 10 months ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆554Updated last month
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆295Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 4 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆324Updated 9 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆266Updated last week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆197Updated last year
• chipsalliance / Cores-VeeR-EH2
  ☆244Updated 2 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆738Updated last week
• BSVLang / Main
  Main page
  ☆128Updated 5 years ago
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆306Updated this week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆162Updated 5 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆279Updated last year
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆273Updated last week
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆241Updated 4 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆297Updated this week
• SpinalHDL / NaxRiscv
  ☆296Updated last week
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆496Updated 2 weeks ago
• f32c / f32c
  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
  ☆413Updated last week
• ucb-bar / berkeley-hardfloat
  ☆347Updated 3 weeks ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆436Updated 3 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆730Updated last week
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆158Updated 3 years ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆299Updated 7 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆532Updated last month