RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
☆379Oct 19, 2023Updated 2 years ago
Alternatives and similar repositories for Flute
Users that are interested in Flute are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆336Jan 23, 2022Updated 4 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆186Apr 4, 2026Updated 3 weeks ago
- Bluespec Compiler (BSC)☆1,103Updated this week
- A place to share libraries and utilities that don't belong in the core bsc repo☆38Apr 4, 2026Updated 3 weeks ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆240Nov 20, 2024Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Main page☆130Feb 12, 2020Updated 6 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,906Apr 23, 2026Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,221Apr 17, 2026Updated 2 weeks ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,170Feb 21, 2026Updated 2 months ago
- A Linux-capable RISC-V multicore for and by the world☆798Apr 24, 2026Updated last week
- RiscyOO: RISC-V Out-of-Order Processor☆171Jul 3, 2020Updated 5 years ago
- 32-bit Superscalar RISC-V CPU☆1,239Sep 18, 2021Updated 4 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,142Mar 11, 2026Updated last month
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆979Nov 15, 2024Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,125Feb 11, 2026Updated 2 months ago
- Host software for running SSITH processors on AWS F1 FPGAs☆20Jul 20, 2021Updated 4 years ago
- RISC-V Formal Verification Framework☆629Apr 6, 2022Updated 4 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆289Mar 30, 2026Updated last month
- SERV - The SErial RISC-V CPU☆1,791Feb 19, 2026Updated 2 months ago
- The OpenPiton Platform☆784Feb 25, 2026Updated 2 months ago
- Working Draft of the RISC-V Debug Specification Standard☆511Apr 8, 2026Updated 3 weeks ago
- A small, light weight, RISC CPU soft core☆1,531Dec 8, 2025Updated 4 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,561Apr 22, 2026Updated last week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆594Apr 20, 2026Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆660Apr 7, 2026Updated 3 weeks ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆160Oct 31, 2024Updated last year
- Common SystemVerilog components☆738Updated this week
- Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...☆55Nov 7, 2021Updated 4 years ago
- pulp_soc is the core building component of PULP based SoCs☆83Mar 10, 2025Updated last year
- VeeR EH1 core☆935May 29, 2023Updated 2 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆308Apr 1, 2026Updated last month
- VeeR EL2 Core☆335Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,859Apr 14, 2026Updated 2 weeks ago
- Rocket Chip Generator☆3,750Apr 21, 2026Updated last week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,541Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆269Nov 6, 2024Updated last year
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,121Jun 27, 2024Updated last year
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆224Jan 11, 2026Updated 3 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆339Dec 11, 2024Updated last year