Alternatives and similar repositories for bsc-contrib

Users that are interested in bsc-contrib are comparing it to the libraries listed below

• B-Lang-org / bdw
  BSC Development Workstation (BDW)
  ☆32Updated last month
• BSVLang / Main
  Main page
  ☆129Updated 5 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 7 months ago
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆89Updated 3 weeks ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆151Updated last month
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆60Updated last year
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆27Updated 5 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆50Updated 3 weeks ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆104Updated last year
• CTSRD-CHERI / bluecheck
  A generic test bench written in Bluespec
  ☆56Updated 5 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 8 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆180Updated 7 months ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 6 years ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 6 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated 2 weeks ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆53Updated 3 weeks ago
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 3 months ago
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆49Updated 2 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆170Updated this week
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆51Updated 10 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆28Updated 2 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last week