Alternatives and similar repositories for hgdb:

Users that are interested in hgdb are comparing it to the libraries listed below

• sifive / duh
  👾 Design ∪ Hardware
  ☆73Updated 2 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 3 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆69Updated last week
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆43Updated 6 months ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆57Updated 2 months ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆150Updated 7 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 8 months ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆39Updated last week
• chipsalliance / fpga-interchange-schema
  ☆52Updated 2 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆79Updated last week
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆42Updated last month
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆51Updated this week
• pulp-platform / svase
  ☆31Updated 3 weeks ago
• Kuree / kratos
  Debuggable hardware generator
  ☆67Updated last year
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆60Updated 5 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆42Updated 3 weeks ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 6 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 8 months ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆23Updated last year
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆99Updated 3 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆25Updated 4 years ago
• rdaly525 / coreir
  ☆102Updated 2 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆79Updated 3 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆142Updated this week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆111Updated 2 years ago
• sifive / chisel-circt
  Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
  ☆70Updated last year
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 2 years ago