Kuree / hgdbLinks
Hardware generator debugger
☆77Updated last year
Alternatives and similar repositories for hgdb
Users that are interested in hgdb are comparing it to the libraries listed below
Sorting:
- Mutation Cover with Yosys (MCY)☆90Updated 3 weeks ago
- A SystemVerilog source file pickler.☆60Updated last year
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆120Updated 8 months ago
- high-performance RTL simulator☆186Updated last year
- An automatic clock gating utility☆52Updated 9 months ago
- Debuggable hardware generator☆70Updated 2 years ago
- Equivalence checking with Yosys☆57Updated 3 weeks ago
- WAL enables programmable waveform analysis.☆163Updated 2 months ago
- SystemVerilog frontend for Yosys☆194Updated last week
- SystemVerilog synthesis tool☆226Updated 10 months ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆55Updated last year
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- ☆104Updated 3 years ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- A SystemVerilog language server based on the Slang library.☆113Updated this week
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- Open source RTL simulation acceleration on commodity hardware☆34Updated 2 years ago
- Testing processors with Random Instruction Generation☆52Updated 2 weeks ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆49Updated last year
- ☆24Updated 4 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- 21st century electronic design automation tools, written in Rust.☆35Updated this week
- ☆33Updated last year
- A tool for synthesizing Verilog programs☆109Updated 5 months ago
- The specification for the FIRRTL language☆62Updated 3 weeks ago
- RISC-V Formal Verification Framework☆177Updated 2 weeks ago
- FPGA tool performance profiling☆105Updated last year