Alternatives and similar repositories for hgdb

Users that are interested in hgdb are comparing it to the libraries listed below

• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 10 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated 2 weeks ago
• Kuree / kratos
  Debuggable hardware generator
  ☆69Updated 2 years ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆173Updated last year
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆110Updated 3 months ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated 2 weeks ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆65Updated 9 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 4 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆117Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆151Updated last week
• rdaly525 / coreir
  ☆103Updated 3 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆208Updated 5 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆53Updated this week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated 2 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• pieter3d / simview
  ☆79Updated last year
• pulp-platform / cheshire-ihp130-o
  ☆49Updated 4 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆83Updated 10 months ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆47Updated 7 months ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆29Updated 2 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆107Updated 4 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• pulp-platform / svase
  ☆32Updated 7 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆42Updated 2 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆37Updated 3 months ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆31Updated last week