Alternatives and similar repositories for hgdb

Users that are interested in hgdb are comparing it to the libraries listed below

• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆88Updated 3 weeks ago
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 6 months ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆182Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆162Updated 3 weeks ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 7 months ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆68Updated last year
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆52Updated 3 weeks ago
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang library.
  ☆70Updated this week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆176Updated this week
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆52Updated last year
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆48Updated last year
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 2 months ago
• BSVLang / Main
  Main page
  ☆128Updated 5 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆219Updated 8 months ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆50Updated last week
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆89Updated last year
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆94Updated last year
• antmicro / sv-bugpoint
  ☆31Updated 2 weeks ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆117Updated 4 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆107Updated 3 months ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆37Updated last month
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago