Alternatives and similar repositories for hgdb

Users that are interested in hgdb are comparing it to the libraries listed below

• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆88Updated last week
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆115Updated 5 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 6 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆166Updated this week
• ucsc-vama / essent
  high-performance RTL simulator
  ☆180Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆157Updated last week
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang library.
  ☆47Updated last week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated 2 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆89Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆66Updated 11 months ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• pieter3d / simview
  ☆85Updated last week
• pulp-platform / cheshire-ihp130-o
  ☆57Updated 6 months ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆48Updated 9 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆215Updated 7 months ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆49Updated 2 weeks ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 5 years ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆31Updated this week
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated last month
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆125Updated last year
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated this week
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆115Updated last year
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 2 months ago