oxidecomputer / cobaltLinks
A collection of common Bluespec interfaces/modules.
☆101Updated last year
Alternatives and similar repositories for cobalt
Users that are interested in cobalt are comparing it to the libraries listed below
Sorting:
- Main page☆31Updated 5 years ago
- Deducing Tock execution flows from Ibex Verilator traces☆70Updated 3 years ago
- Where Lions Roam: RISC-V on the VELDT☆260Updated 10 months ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 2 years ago
- Fearless hardware design☆176Updated last month
- A computer for human beings.☆44Updated 7 months ago
- Glacial - microcoded RISC-V core designed for low FPGA resource utilization☆85Updated 5 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆34Updated 3 years ago
- Documenting Lattice's 28nm FPGA parts☆143Updated last year
- An HDL embedded in Rust.☆199Updated last year
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆219Updated last year
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- A core language for rule-based hardware design 🦑☆156Updated last week
- The SiFive wake build tool☆90Updated last week
- Hardware definition language that compiles to Verilog☆106Updated 3 years ago
- Betrusted embedded controller (UP5K)☆45Updated last year
- A place to share libraries and utilities that don't belong in the core bsc repo☆35Updated 3 months ago
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆111Updated this week
- A 16-bit CPU and self-hosting Forth system for the Lattice ICE40 FPGA, written in Haskell.☆58Updated 4 years ago
- Formal specification and verification of hardware, especially for security and privacy.☆126Updated 3 years ago
- ☆56Updated 2 years ago
- BSC Development Workstation (BDW)☆29Updated 7 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆32Updated this week
- Manythread RISC-V overlay for FPGA clusters☆38Updated 2 years ago
- System on Chip toolkit for Amaranth HDL☆91Updated 8 months ago
- Main page☆126Updated 5 years ago
- Hot Reconfiguration Technology demo☆40Updated 2 years ago
- Locus site for Public Review of Several RISC-V ISA Formal Specs☆73Updated 5 years ago
- End-to-end synthesis and P&R toolchain☆85Updated 2 weeks ago
- Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference☆73Updated 2 years ago