rsnikhil / ICFP2020_Bluespec_TutorialLinks
Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
☆73Updated 2 years ago
Alternatives and similar repositories for ICFP2020_Bluespec_Tutorial
Users that are interested in ICFP2020_Bluespec_Tutorial are comparing it to the libraries listed below
Sorting:
- A core language for rule-based hardware design 🦑☆160Updated 3 months ago
- A collection of reusable Clash designs/examples☆53Updated last year
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆159Updated 2 months ago
- Main page☆128Updated 5 years ago
- Haskell library for hardware description☆104Updated last month
- A generic test bench written in Bluespec☆55Updated 4 years ago
- A formal semantics of the RISC-V ISA in Haskell☆170Updated 2 years ago
- Time-sensitive affine types for predictable hardware generation☆145Updated last week
- Formal specification of RISC-V Instruction Set☆101Updated 5 years ago
- Bluespec BSV HLHDL tutorial☆110Updated 9 years ago
- A RiscV processor implementing the RV32I instruction set written in Clash☆53Updated 7 years ago
- The source code to the Voss II Hardware Verification Suite☆56Updated last week
- Galois RISC-V ISA Formal Tools☆61Updated last month
- A place to share libraries and utilities that don't belong in the core bsc repo☆36Updated 6 months ago
- Formal specification and verification of hardware, especially for security and privacy.☆126Updated 3 years ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆93Updated 2 weeks ago
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆83Updated 2 months ago
- ☆40Updated 4 years ago
- An introductory guide to Bluespec (BSV)☆64Updated 6 years ago
- Manythread RISC-V overlay for FPGA clusters☆38Updated last week
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆54Updated this week
- Verilog development and verification project for HOL4☆27Updated 4 months ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆115Updated 4 months ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆373Updated last year
- RISC-V Formal Verification Framework☆150Updated this week
- Chisel/Firrtl execution engine☆154Updated last year
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆13Updated 8 years ago
- ☆30Updated 4 years ago
- Bluespec Compiler (BSC)☆1,043Updated 3 weeks ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆326Updated 3 years ago