Alternatives and similar repositories for ICFP2020_Bluespec_Tutorial

Users that are interested in ICFP2020_Bluespec_Tutorial are comparing it to the libraries listed below

• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆156Updated last month
• mit-plv / kami
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆155Updated 2 weeks ago
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• blarney-lang / blarney
  Haskell library for hardware description
  ☆104Updated last month
• rsnikhil / Forvis_RISCV-ISA-Spec
  Formal specification of RISC-V Instruction Set
  ☆100Updated 5 years ago
• adamwalker / clash-utils
  A collection of reusable Clash designs/examples
  ☆52Updated last year
• CTSRD-CHERI / bluecheck
  A generic test bench written in Bluespec
  ☆53Updated 4 years ago
• mit-plv / riscv-semantics
  A formal semantics of the RISC-V ISA in Haskell
  ☆167Updated last year
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆55Updated 2 weeks ago
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆105Updated 9 years ago
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆145Updated this week
• vegaluisjose / reticle
  ☆40Updated 3 years ago
• ymherklotz / vericert
  A formally verified high-level synthesis tool based on CompCert and written in Coq.
  ☆92Updated last year
• CakeML / hardware
  Verilog development and verification project for HOL4
  ☆26Updated 2 months ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆35Updated 3 months ago
• GaloisInc / grift
  Galois RISC-V ISA Formal Tools
  ☆60Updated 3 months ago
• adamwalker / clash-riscv
  A RiscV processor implementing the RV32I instruction set written in Clash
  ☆53Updated 7 years ago
• project-oak / silveroak
  Formal specification and verification of hardware, especially for security and privacy.
  ☆126Updated 3 years ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆39Updated this week
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆78Updated last week
• braibant / Synthesis
  ☆21Updated 9 years ago
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 7 years ago
• kcamenzind / BluespecIntroGuide
  An introductory guide to Bluespec (BSV)
  ☆62Updated 6 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 2 months ago
• sangwoojun / ulx3s_bsv
  Bluespec environment for working with the ulx3s board and its lattice ecp5 fpga
  ☆11Updated 4 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆142Updated last month
• clash-lang / clash-starters
  Projects to get started with Clash
  ☆30Updated 6 months ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• rdaly525 / coreir
  ☆103Updated 3 years ago
• rsnikhil / goParseBSV
  A standalone parser for BSV (Bluespec SystemVerilog) written in Go
  ☆13Updated 8 years ago