Alternatives and similar repositories for Learn_Bluespec_and_RISCV_Design

Users that are interested in Learn_Bluespec_and_RISCV_Design are comparing it to the libraries listed below

• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆162Updated this week
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆110Updated 9 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆215Updated 7 months ago
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆225Updated 3 weeks ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆108Updated 5 months ago
• BSVLang / Main
  Main page
  ☆128Updated 5 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆185Updated this week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆200Updated last year
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆156Updated 11 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 5 months ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆105Updated 2 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆233Updated 11 months ago
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆113Updated 4 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆231Updated last week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆122Updated 2 weeks ago
• tenstorrent / whisper
  ☆59Updated last week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆166Updated last week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆157Updated last week
• bsc-loca / sargantana
  ☆109Updated 2 months ago
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆141Updated this week
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆217Updated this week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆164Updated 5 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆190Updated last year
• ucsc-vama / essent
  high-performance RTL simulator
  ☆180Updated last year
• openhwgroup / cv-hpdcache-verif
  Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
  ☆18Updated 8 months ago
• riscv-software-src / riscof
  ☆92Updated last month
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆50Updated last year
• SpinalHDL / NaxRiscv
  ☆298Updated last month
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 5 months ago