rsnikhil / Learn_Bluespec_and_RISCV_DesignLinks
Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
☆84Updated last week
Alternatives and similar repositories for Learn_Bluespec_and_RISCV_Design
Users that are interested in Learn_Bluespec_and_RISCV_Design are comparing it to the libraries listed below
Sorting:
- RISC-V Formal Verification Framework☆162Updated this week
- Bluespec BSV HLHDL tutorial☆110Updated 9 years ago
- SystemVerilog synthesis tool☆215Updated 7 months ago
- Open-source RTL logic simulator with CUDA acceleration☆225Updated 3 weeks ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆108Updated 5 months ago
- Main page☆128Updated 5 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆185Updated this week
- RISC-V Torture Test☆200Updated last year
- A dynamic verification library for Chisel.☆156Updated 11 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 5 months ago
- A tool for synthesizing Verilog programs☆105Updated 2 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆233Updated 11 months ago
- Self checking RISC-V directed tests☆113Updated 4 months ago
- A Fast, Low-Overhead On-chip Network☆231Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆122Updated 2 weeks ago
- ☆59Updated last week
- SystemVerilog frontend for Yosys☆166Updated last week
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- WAL enables programmable waveform analysis.☆157Updated last week
- ☆109Updated 2 months ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆141Updated this week
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆217Updated this week
- RiscyOO: RISC-V Out-of-Order Processor☆164Updated 5 years ago
- ☆190Updated last year
- high-performance RTL simulator☆180Updated last year
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆18Updated 8 months ago
- ☆92Updated last month
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆50Updated last year
- ☆298Updated last month
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 5 months ago