Alternatives and similar repositories for Learn_Bluespec_and_RISCV_Design:

Users that are interested in Learn_Bluespec_and_RISCV_Design are comparing it to the libraries listed below

• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆127Updated 3 weeks ago
• BSVLang / Main
  Main page
  ☆125Updated 5 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆142Updated this week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 8 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆165Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 9 months ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆85Updated 10 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆166Updated 6 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆145Updated 3 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆89Updated this week
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆64Updated 2 weeks ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆60Updated 5 months ago
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆100Updated last week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆226Updated 3 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆30Updated 9 months ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆157Updated last month
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆140Updated 3 months ago
• chipsalliance / uvm-verilator
  ☆86Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆67Updated 10 months ago
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆98Updated 8 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆177Updated 7 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆144Updated this week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆154Updated 4 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆177Updated this week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆103Updated this week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated last week
• riscv-ovpsim / imperas-riscv-tests
  ☆167Updated last year
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆84Updated this week
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆78Updated 4 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 3 months ago