Alternatives and similar repositories for Learn_Bluespec_and_RISCV_Design

Users that are interested in Learn_Bluespec_and_RISCV_Design are comparing it to the libraries listed below

• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆141Updated last week
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆95Updated last month
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆105Updated 9 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆175Updated last month
• chipsalliance / uvm-verilator
  ☆96Updated last year
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆163Updated last week
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆84Updated this week
• sifferman / schematics
  Examples of how to Generate Schematics from SystemVerilog Synthesis Tools
  ☆22Updated last year
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 7 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆211Updated last week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆196Updated 11 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆128Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆198Updated 3 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆178Updated 6 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆179Updated last year
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆112Updated last week
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆113Updated this week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆88Updated last week
• bsc-loca / sargantana
  ☆104Updated last month
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆158Updated 4 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆154Updated 2 weeks ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆101Updated last month
• tenstorrent / whisper
  ☆46Updated last week
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆108Updated 3 weeks ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆67Updated last year
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆174Updated 2 months ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 2 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated last month