A core language for rule-based hardware design 🦑
☆173Dec 10, 2025Updated 2 months ago
Alternatives and similar repositories for koika
Users that are interested in koika are comparing it to the libraries listed below
Sorting:
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆164Nov 20, 2025Updated 3 months ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆38Feb 16, 2026Updated 2 weeks ago
- Bluespec Compiler (BSC)☆1,081Feb 16, 2026Updated 2 weeks ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆36Jan 16, 2025Updated last year
- Build an educational formally verified version of the Nand 2 Tetris course using Coq (and other formal tools).☆58Dec 24, 2021Updated 4 years ago
- Intermediate Language (IL) for Hardware Accelerator Generators☆582Updated this week
- A formal semantics of the RISC-V ISA in Haskell☆173Aug 13, 2023Updated 2 years ago
- A generic test bench written in Bluespec☆57Dec 15, 2020Updated 5 years ago
- ☆18May 1, 2020Updated 5 years ago
- ☆17Mar 26, 2025Updated 11 months ago
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- An open bibliography of machine learning for formal proof papers☆32Sep 30, 2023Updated 2 years ago
- Formal specification and verification of hardware, especially for security and privacy.☆128May 19, 2022Updated 3 years ago
- Fearless hardware design☆197Aug 20, 2025Updated 6 months ago
- Fluid Pipelines☆11May 4, 2018Updated 7 years ago
- The source code to the Voss II Hardware Verification Suite☆56Feb 16, 2026Updated 2 weeks ago
- (System)Verilog to Chisel translator☆116May 20, 2022Updated 3 years ago
- Verilog development and verification project for HOL4☆28Apr 25, 2025Updated 10 months ago
- CoreIR Symbolic Analyzer☆74Oct 27, 2020Updated 5 years ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆98Jan 29, 2026Updated last month
- RISC-V Specification in Coq☆116Jan 5, 2026Updated last month
- RTLCheck☆25Oct 9, 2018Updated 7 years ago
- ☆52Jan 16, 2025Updated last year
- Relation algebra library for Coq☆50Feb 17, 2026Updated 2 weeks ago
- ☆40Sep 17, 2021Updated 4 years ago
- ☆16Jan 5, 2022Updated 4 years ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆65Updated this week
- A framework for formally verifying hardware security modules to be free of hardware, software, and timing side-channel vulnerabilities 🔏☆40Nov 29, 2025Updated 3 months ago
- Gallina to Bedrock2 compilation toolkit☆65Updated this week
- 21st century electronic design automation tools, written in Rust.☆36Feb 23, 2026Updated last week
- A work-in-progress language and compiler for verified low-level programming☆323Updated this week
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆38Mar 30, 2021Updated 4 years ago
- Main page☆129Feb 12, 2020Updated 6 years ago
- Low Level Hardware Description — A foundation for building hardware design tools.☆427Apr 20, 2022Updated 3 years ago
- Time-sensitive affine types for predictable hardware generation☆148Jan 5, 2026Updated last month
- Linearizability Hoare Logic☆17Feb 9, 2026Updated 3 weeks ago
- Functions and proofs about game trees in Rocq, implemented as rose trees.☆16Updated this week
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago
- Verified Extraction from Rocq to OCaml/Malfunction☆14May 23, 2025Updated 9 months ago