mit-plv / koikaLinks
A core language for rule-based hardware design 🦑
☆154Updated 7 months ago
Alternatives and similar repositories for koika
Users that are interested in koika are comparing it to the libraries listed below
Sorting:
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆154Updated 8 months ago
- A formal semantics of the RISC-V ISA in Haskell☆165Updated last year
- Time-sensitive affine types for predictable hardware generation☆143Updated 10 months ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆92Updated 11 months ago
- The source code to the Voss II Hardware Verification Suite☆56Updated last month
- A generic test bench written in Bluespec☆52Updated 4 years ago
- Verilog development and verification project for HOL4☆26Updated last month
- Formal specification of RISC-V Instruction Set☆100Updated 4 years ago
- Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference☆73Updated 2 years ago
- Formal specification and verification of hardware, especially for security and privacy.☆126Updated 3 years ago
- ☆40Updated 3 years ago
- RISC-V Specification in Coq☆114Updated 4 months ago
- CHERI-RISC-V model written in Sail☆59Updated last month
- Fearless hardware design☆176Updated last month
- A Modeling and Verification Platform for SoCs using ILAs☆77Updated 10 months ago
- CoreIR Symbolic Analyzer☆72Updated 4 years ago
- Haskell library for hardware description☆103Updated 6 months ago
- ☆103Updated 2 years ago
- Galois RISC-V ISA Formal Tools☆58Updated 2 months ago
- RISC-V Formal Verification Framework☆139Updated this week
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆76Updated 8 months ago
- Manythread RISC-V overlay for FPGA clusters☆38Updated 2 years ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆72Updated this week
- Main page☆126Updated 5 years ago
- A Hardware Pipeline Description Language☆44Updated last year
- ☆26Updated 2 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆141Updated this week
- Pono: A flexible and extensible SMT-based model checker☆102Updated this week
- FPGA synthesis tool powered by program synthesis☆48Updated last week