Alternatives and similar repositories for koika

Users that are interested in koika are comparing it to the libraries listed below

• mit-plv / kami
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆158Updated last month
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆145Updated this week
• ymherklotz / vericert
  A formally verified high-level synthesis tool based on CompCert and written in Coq.
  ☆93Updated last week
• mit-plv / riscv-semantics
  A formal semantics of the RISC-V ISA in Haskell
  ☆170Updated 2 years ago
• project-oak / silveroak
  Formal specification and verification of hardware, especially for security and privacy.
  ☆126Updated 3 years ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated last month
• CakeML / hardware
  Verilog development and verification project for HOL4
  ☆27Updated 4 months ago
• vegaluisjose / reticle
  ☆40Updated 3 years ago
• rsnikhil / Forvis_RISCV-ISA-Spec
  Formal specification of RISC-V Instruction Set
  ☆101Updated 5 years ago
• rsnikhil / ICFP2020_Bluespec_Tutorial
  Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
  ☆73Updated 2 years ago
• CTSRD-CHERI / bluecheck
  A generic test bench written in Bluespec
  ☆54Updated 4 years ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆64Updated 2 months ago
• GaloisInc / grift
  Galois RISC-V ISA Formal Tools
  ☆61Updated last month
• mit-plv / riscv-coq
  RISC-V Specification in Coq
  ☆116Updated last week
• cucapra / filament
  Fearless hardware design
  ☆179Updated 3 weeks ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆52Updated 2 months ago
• blarney-lang / blarney
  Haskell library for hardware description
  ☆104Updated 3 weeks ago
• riscvarchive / ISA_Formal_Spec_Public_Review
  Locus site for Public Review of Several RISC-V ISA Formal Specs
  ☆75Updated 5 years ago
• BSVLang / Main
  Main page
  ☆128Updated 5 years ago
• POETSII / tinsel
  Manythread RISC-V overlay for FPGA clusters
  ☆38Updated this week
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 4 years ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆36Updated 5 months ago
• stanford-centaur / pono
  Pono: A flexible and extensible SMT-based model checker
  ☆109Updated this week
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆81Updated this week
• cucapra / diospyros
  Search-based compiler for high-performance DSP programming
  ☆67Updated 10 months ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• opencompl / lean-mlir
  A minimal development of SSA theory
  ☆171Updated last week
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆77Updated last year
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆108Updated 9 years ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆82Updated 2 months ago