Alternatives and similar repositories for BSV_Tutorial_cn:

Users that are interested in BSV_Tutorial_cn are comparing it to the libraries listed below

• WangXuan95 / USTC-RVSoC
  An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
  ☆398Updated last year
• Nitcloud / Digital-IDE
  在vscode上的数字设计开发插件
  ☆368Updated 2 years ago
• WangXuan95 / FPGA-JPEG-LS-encoder
  An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码…
  ☆242Updated 7 months ago
• WangXuan95 / FPGA-SDcard-Reader
  An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
  ☆290Updated last year
• WangXuan95 / FPGA-DDR-SDRAM
  An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
  ☆174Updated last year
• WangXuan95 / Xilinx-FPGA-PCIe-XDMA-Tutorial
  Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
  ☆581Updated last year
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆194Updated last month
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆103Updated 2 years ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆144Updated 2 months ago
• WangXuan95 / FPGA-FixedPoint
  Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…
  ☆175Updated last year
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆146Updated 2 years ago
• viduraakalanka / HDL-Bits-Solutions
  This is a repository containing solutions to the problem statements given in HDL Bits website.
  ☆348Updated last year
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆632Updated 2 months ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,029Updated 7 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆571Updated 8 months ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆205Updated 8 months ago
• cnrv / riscv-soc-book
  关于RISC-V你所需要知道的一切
  ☆557Updated 2 years ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,692Updated last month
• WangXuan95 / Zynq-Tutorial
  使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例
  ☆98Updated 7 months ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆936Updated this week
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆801Updated last month
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆441Updated 3 years ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆826Updated 2 weeks ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,256Updated 2 weeks ago
• cxdzyq1110 / NPU_on_FPGA
  在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。
  ☆237Updated 6 years ago
• WangXuan95 / FPGA-UART
  This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…
  ☆188Updated last year
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆394Updated 9 months ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆251Updated 2 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆133Updated 10 months ago
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆260Updated last year