WangXuan95 / BSV_Tutorial_cnLinks
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。
☆601Updated 2 years ago
Alternatives and similar repositories for BSV_Tutorial_cn
Users that are interested in BSV_Tutorial_cn are comparing it to the libraries listed below
Sorting:
- An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。☆428Updated 2 years ago
- 在vscode上的数字设计开发插件☆394Updated 3 years ago
- An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码…☆306Updated last year
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆774Updated 2 years ago
- AXI协议规范中文翻译版☆171Updated 3 years ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆1,049Updated this week
- Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…☆223Updated 2 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆294Updated 2 years ago
- An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器,可以从FAT16或FAT32格式的SD卡中读取文件。☆330Updated 2 years ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,107Updated last year
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆202Updated 2 years ago
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆369Updated 2 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆603Updated last year
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆113Updated 3 years ago
- 使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例☆119Updated last year
- Collect some IC textbooks for learning.☆182Updated 3 years ago
- ☆66Updated 2 years ago
- Documentation for XiangShan☆432Updated this week
- A template project for beginning new Chisel work☆689Updated last week
- ☆220Updated 7 months ago
- ☆153Updated 2 months ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 4 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆151Updated last year
- An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA comm…☆862Updated last year
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆126Updated 3 years ago
- Vivado诸多IP,包括图像处理等☆234Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,487Updated last week
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆223Updated this week
- An FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器,用来进行无损图像压缩。☆102Updated last year
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆417Updated 4 months ago