Alternatives and similar repositories for BSV_Tutorial_cn

Users that are interested in BSV_Tutorial_cn are comparing it to the libraries listed below

• WangXuan95 / USTC-RVSoC
  An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
  ☆418Updated 2 years ago
• Nitcloud / Digital-IDE
  在vscode上的数字设计开发插件
  ☆387Updated 2 years ago
• WangXuan95 / FPGA-UART
  This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…
  ☆256Updated 2 years ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆995Updated last month
• WangXuan95 / Xilinx-FPGA-PCIe-XDMA-Tutorial
  Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
  ☆699Updated 2 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆163Updated 3 years ago
• WangXuan95 / FPGA-JPEG-LS-encoder
  An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码…
  ☆283Updated last year
• WangXuan95 / FPGA-FixedPoint
  Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…
  ☆211Updated 2 years ago
• viduraakalanka / HDL-Bits-Solutions
  This is a repository containing solutions to the problem statements given in HDL Bits website.
  ☆363Updated 2 years ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆591Updated last year
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆307Updated 7 years ago
• WangXuan95 / FPGA-DDR-SDRAM
  An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
  ☆192Updated 2 years ago
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆426Updated last week
• WangXuan95 / FPGA-SDcard-Reader
  An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
  ☆317Updated 2 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆61Updated 3 years ago
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆123Updated 3 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆179Updated 11 months ago
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆662Updated 2 weeks ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,065Updated last year
• WangXuan95 / Zynq-Tutorial
  使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例
  ☆110Updated last year
• xiaop1 / Verilog-Practice
  HDLBits website practices & solutions
  ☆752Updated last year
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆111Updated 3 years ago
• lizhirui / DreamCore
  ☆64Updated 3 years ago
• DawnCarol / DawnCarol
  ☆206Updated 5 months ago
• OSCPU / NutShell-doc
  ☆123Updated 3 years ago
• cxdzyq1110 / NPU_on_FPGA
  在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。
  ☆266Updated 7 years ago
• OSCPU / ysyx-workbench
  ☆156Updated last week
• RV-BOSC / OpenNoC
  ☆195Updated 3 months ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆149Updated last month
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆861Updated last week