Alternatives and similar repositories for Bluespec_BSV_Tutorial:

Users that are interested in Bluespec_BSV_Tutorial are comparing it to the libraries listed below

• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆150Updated 6 months ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆74Updated 9 years ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆92Updated last week
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆156Updated 4 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆174Updated 9 months ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆82Updated last year
• ucb-bar / sha3
  ☆81Updated last year
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆137Updated this week
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆72Updated 7 months ago
• chipsalliance / uvm-verilator
  ☆92Updated last year
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆122Updated last year
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆193Updated 9 months ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated 3 weeks ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆113Updated 2 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆81Updated last year
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆178Updated 5 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆65Updated 10 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆62Updated this week
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆120Updated 10 months ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆157Updated 10 months ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆174Updated 2 years ago