Bluespec BSV HLHDL tutorial
☆116Mar 29, 2016Updated 10 years ago
Alternatives and similar repositories for Bluespec_BSV_Tutorial
Users that are interested in Bluespec_BSV_Tutorial are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Main page☆133Jul 13, 2026Updated last week
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆104Jul 3, 2026Updated 3 weeks ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆17Jul 17, 2016Updated 10 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Sep 15, 2017Updated 8 years ago
- Bluespec Compiler (BSC)☆1,132Updated this week
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- An introductory guide to Bluespec (BSV)☆69May 4, 2019Updated 7 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆170Jul 3, 2020Updated 6 years ago
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 2 years ago
- BSC Development Workstation (BDW)☆33May 1, 2026Updated 2 months ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆35Dec 10, 2021Updated 4 years ago
- ☆15Jun 1, 2019Updated 7 years ago
- Miscellaneous components for bluespec☆11Nov 18, 2024Updated last year
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆25Aug 23, 2021Updated 4 years ago
- Bluespec environment for working with the ulx3s board and its lattice ecp5 fpga☆15Mar 9, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A generic test bench written in Bluespec☆57Dec 15, 2020Updated 5 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆40May 1, 2026Updated 2 months ago
- Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference☆80Nov 24, 2022Updated 3 years ago
- Development area for another repo: Learn_Bluespec_and_RISCV_Design☆13Jun 28, 2026Updated 3 weeks ago
- 一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。☆610Sep 15, 2023Updated 2 years ago
- The BERI and CHERI processor and hardware platform☆51Mar 27, 2017Updated 9 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆13May 17, 2018Updated 8 years ago
- Graph accelerator on FPGAs and ASICs☆11Aug 16, 2018Updated 7 years ago
- Learn the Design of a 6-stage pipelined RISC-V CPU☆16Oct 22, 2025Updated 9 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators☆10Sep 7, 2015Updated 10 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆74Apr 4, 2019Updated 7 years ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆11May 24, 2019Updated 7 years ago
- An open-source custom cache generator.☆37Mar 14, 2024Updated 2 years ago
- Kami - a DSL for designing Hardware in Coq, and the associated semantics and theorems for proving its correctness. Kami is inspired by Bl…☆223Aug 31, 2020Updated 5 years ago
- Hardware Description Languages☆1,162Jul 9, 2026Updated 2 weeks ago
- ☆15Feb 6, 2021Updated 5 years ago
- Automatic generation of architecture-level models for hardware from its RTL design.☆16Apr 12, 2023Updated 3 years ago
- FPGA-based HyperLogLog Accelerator☆12Jul 13, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆341Jan 23, 2022Updated 4 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Mar 6, 2018Updated 8 years ago
- The hardware implementation of UDP in Bluespec SystemVerilog☆14Jun 3, 2024Updated 2 years ago
- ☆15Nov 28, 2020Updated 5 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆675Jul 7, 2026Updated 2 weeks ago
- ☆32May 27, 2018Updated 8 years ago
- ☆11Feb 15, 2022Updated 4 years ago