drom / awesome-hdl

Related projects ⓘ

Alternatives and complementary repositories for awesome-hdl

• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆493Updated last year
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,206Updated 2 weeks ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆645Updated this week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆865Updated 3 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆624Updated this week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆822Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆966Updated 4 months ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,442Updated last week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆771Updated 2 weeks ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,193Updated 6 months ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,305Updated last month
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆526Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,113Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆564Updated 3 weeks ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆838Updated this week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,381Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆518Updated this week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆643Updated last month
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆742Updated this week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆585Updated 2 years ago
• KastnerRG / pp4fpgas
  Parallel Programming for FPGAs -- An open-source high-level synthesis book
  ☆795Updated last week
• cocotb / cocotb
  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
  ☆1,814Updated this week
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,017Updated this week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆407Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆490Updated 10 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆626Updated this week
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆731Updated 3 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆438Updated 3 weeks ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆588Updated 4 months ago
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆551Updated 3 years ago