Alternatives and similar repositories for awesome-hdl:

Users that are interested in awesome-hdl are comparing it to the libraries listed below

• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆518Updated last year
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆864Updated last year
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆820Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,256Updated last week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆972Updated 3 years ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆606Updated last week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆671Updated last week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,371Updated last month
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆593Updated last week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,500Updated last month
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆647Updated 4 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆904Updated 4 months ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,263Updated 10 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆598Updated 2 years ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,514Updated last week
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆739Updated 7 months ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆887Updated last week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆435Updated 2 weeks ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆883Updated 4 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆669Updated 3 weeks ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,242Updated last week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆709Updated 3 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆402Updated 6 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,029Updated last month
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,081Updated last month
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆673Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆529Updated last month
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆563Updated 7 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆486Updated 4 months ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,018Updated 6 months ago