Alternatives and similar repositories for awesome-hdl

Users that are interested in awesome-hdl are comparing it to the libraries listed below

• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆578Updated 2 years ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆688Updated last month
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,380Updated 2 weeks ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆734Updated 2 weeks ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆483Updated last week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,034Updated last week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆692Updated 2 weeks ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,494Updated 3 weeks ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,166Updated 4 years ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,723Updated 3 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆473Updated 2 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆629Updated 2 weeks ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆753Updated last month
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,156Updated 7 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆678Updated 5 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,719Updated 2 weeks ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,201Updated last week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆917Updated 2 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆615Updated 8 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆620Updated 3 years ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆681Updated 3 weeks ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,447Updated 3 weeks ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆889Updated last month
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,116Updated this week
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆764Updated last year
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆754Updated 3 months ago
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆739Updated 11 months ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆417Updated last year
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆434Updated 3 years ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆951Updated last year