Hardware Description Languages
☆1,151Apr 6, 2026Updated 2 months ago
Alternatives and similar repositories for awesome-hdl
Users that are interested in awesome-hdl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆609Jan 3, 2026Updated 5 months ago
- A curated list of awesome resources for HDL design and verification☆174Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,420Jun 8, 2026Updated last week
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆225May 19, 2026Updated 3 weeks ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆475Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- An abstraction library for interfacing EDA tools☆771Apr 24, 2026Updated last month
- cocotb: Python-based chip (RTL) verification☆2,407Updated this week
- A curated list of awesome HDL, libraries, typical implementation and references.☆37Oct 19, 2016Updated 9 years ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,858Jun 9, 2026Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆669May 11, 2026Updated last month
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆458Apr 5, 2026Updated 2 months ago
- Scala based HDL☆2,000Updated this week
- SystemVerilog to Verilog conversion☆736Mar 28, 2026Updated 2 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆463May 31, 2026Updated 2 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Test suite designed to check compliance with the SystemVerilog standard.☆378Updated this week
- Verilog library for ASIC and FPGA designers☆1,421May 8, 2024Updated 2 years ago
- Code generation tool for control and status registers☆463May 30, 2026Updated 2 weeks ago
- Verilator open-source SystemVerilog simulator and lint system☆3,679Updated this week
- Yosys Open SYnthesis Suite☆4,531Updated this week
- List of awesome open source hardware tools, generators, and reusable designs☆2,346Mar 2, 2026Updated 3 months ago
- magma circuits☆263Oct 19, 2024Updated last year
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,166Feb 11, 2026Updated 4 months ago
- A modern hardware definition language and toolchain based on Python☆2,028May 25, 2026Updated 3 weeks ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Bluespec Compiler (BSC)☆1,118Updated this week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆328Jun 30, 2025Updated 11 months ago
- SystemVerilog compiler and language services☆1,068Jun 9, 2026Updated last week
- SERV - The SErial RISC-V CPU☆1,812Feb 19, 2026Updated 3 months ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆830May 14, 2026Updated last month
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆723Updated this week
- Common SystemVerilog components☆757Jun 5, 2026Updated last week
- Build your hardware, easily!☆3,927Jun 9, 2026Updated last week
- Chisel: A Modern Hardware Design Language☆4,680Jun 4, 2026Updated last week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 😎 A curated list of awesome RISC-V implementations☆143Mar 12, 2023Updated 3 years ago
- A curated list of awesome open source hardware design tools☆88Jun 20, 2025Updated 11 months ago
- HDL symbol generator☆203Feb 2, 2023Updated 3 years ago
- draws an SVG schematic from a JSON netlist☆797Jan 25, 2024Updated 2 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,203Jun 27, 2024Updated last year
- SystemVerilog linter☆386Nov 6, 2025Updated 7 months ago
- Digital Design with Chisel☆920Apr 30, 2026Updated last month