drom / awesome-hdl

Related projects: ⓘ

• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆480Updated last year
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,164Updated last week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆816Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆535Updated 2 weeks ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,375Updated 3 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆810Updated last year
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆840Updated 3 years ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆574Updated 2 years ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,268Updated 3 weeks ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆622Updated 3 weeks ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆619Updated 9 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,338Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,048Updated last month
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆494Updated this week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆740Updated last month
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆926Updated 2 months ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,155Updated 4 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆597Updated 2 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆357Updated last week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆626Updated last month
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,002Updated this week
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆812Updated 2 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆720Updated last month
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆470Updated 8 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆838Updated 4 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆389Updated this week
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,321Updated this week
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆818Updated this week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆498Updated 2 weeks ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆997Updated 3 weeks ago