drom / awesome-hdlLinks
Hardware Description Languages
☆1,064Updated 2 months ago
Alternatives and similar repositories for awesome-hdl
Users that are interested in awesome-hdl are comparing it to the libraries listed below
Sorting:
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆554Updated 2 years ago
- SystemVerilog to Verilog conversion☆665Updated 2 months ago
- An abstraction library for interfacing EDA tools☆712Updated 2 weeks ago
- Modular hardware build system☆1,077Updated this week
- An Open-source FPGA IP Generator☆993Updated this week
- Common SystemVerilog components☆654Updated last week
- Multi-platform nightly builds of open source digital design and verification tools☆1,157Updated this week
- SERV - The SErial RISC-V CPU☆1,639Updated 3 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,336Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,117Updated 3 months ago
- VeeR EH1 core☆894Updated 2 years ago
- A Linux-capable RISC-V multicore for and by the world☆731Updated 3 weeks ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆674Updated last month
- 32-bit Superscalar RISC-V CPU☆1,091Updated 3 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆605Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆467Updated last week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,628Updated 2 weeks ago
- The OpenPiton Platform☆729Updated 2 weeks ago
- lowRISC Style Guides☆453Updated 3 months ago
- Bus bridges and other odds and ends☆587Updated 5 months ago
- RISC-V Formal Verification Framework☆609Updated 3 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,369Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆933Updated 10 months ago
- cocotb: Python-based chip (RTL) verification☆2,075Updated this week
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆724Updated 7 months ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆642Updated 2 weeks ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,629Updated 2 weeks ago
- Random instruction generator for RISC-V processor verification☆1,166Updated 3 months ago
- A list of resources related to the open-source FPGA projects☆425Updated 2 years ago
- A small, light weight, RISC CPU soft core☆1,459Updated last month