liang-aquarius / ca_modelView external linksLinks
A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are coming.
☆17Sep 5, 2019Updated 6 years ago
Alternatives and similar repositories for ca_model
Users that are interested in ca_model are comparing it to the libraries listed below
Sorting:
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆33Feb 3, 2026Updated last week
- ☆36Apr 20, 2021Updated 4 years ago
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 9 months ago
- A Toy-Purpose TPU Simulator☆21Jun 7, 2024Updated last year
- UVM verification platform for DW_apb_i2c IP core(Master Mode)☆11Aug 21, 2023Updated 2 years ago
- Digital IC design and vlsi notes☆12Jun 24, 2020Updated 5 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆24Updated this week
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 3 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆31Dec 24, 2025Updated last month
- ☆15Nov 12, 2023Updated 2 years ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 5 months ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Jan 12, 2026Updated last month
- SoC design & prototyping☆16Jun 13, 2025Updated 8 months ago
- NoC simulation using gem5 (a simple tul)☆14Mar 23, 2024Updated last year
- CNN accelerator using NoC architecture☆17Dec 6, 2018Updated 7 years ago
- A small Neural Network Processor for Edge devices.☆15Nov 22, 2022Updated 3 years ago
- SystemC training aimed at TLM.☆35Jul 31, 2020Updated 5 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Jul 2, 2022Updated 3 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆24Mar 13, 2025Updated 11 months ago
- Lab assignments for the Agile Hardware Design course☆18Nov 14, 2025Updated 3 months ago
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆23Jun 16, 2025Updated 7 months ago
- ☆23Nov 27, 2025Updated 2 months ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆19Aug 13, 2018Updated 7 years ago
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- ☆20Dec 19, 2025Updated last month
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Aug 10, 2018Updated 7 years ago
- Open-source non-blocking L2 cache☆52Feb 3, 2026Updated last week
- C++ RTL simulator for EIE(https://arxiv.org/abs/1602.01528)☆23Mar 17, 2021Updated 4 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- This is the open-source version of TinyTS. The code is dirty so far. We may clean the code in the future.☆19Aug 11, 2025Updated 6 months ago
- make your verilog DUT test more smart☆22Sep 9, 2016Updated 9 years ago
- Open-source Neural Processing Unit (NPU) from China ❤☆35Jan 29, 2025Updated last year
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- Network on Chip for MPSoC☆28Jan 27, 2026Updated 2 weeks ago