liang-aquarius / ca_model
A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are coming.
☆14Updated 5 years ago
Alternatives and similar repositories for ca_model
Users that are interested in ca_model are comparing it to the libraries listed below
Sorting:
- A simple cycle-accurate DaDianNao simulator☆13Updated 6 years ago
- ☆35Updated 4 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆11Updated 5 years ago
- ☆27Updated 5 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆20Updated 3 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆26Updated 2 weeks ago
- Learn NVDLA by SOMNIA☆33Updated 5 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆15Updated 2 years ago
- A scalable Eyeriss model in SystemC.☆27Updated 2 years ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆14Updated 3 weeks ago
- ☆30Updated last month
- Fork of the gem5 simulator with Garnet2.0 and DSENT extensions☆10Updated 6 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- ☆8Updated last year
- A Toy-Purpose TPU Simulator☆18Updated 11 months ago
- ☆14Updated last year
- Express DLA implementation for FPGA, revised based on NVDLA.☆9Updated 5 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆34Updated 4 months ago
- ☆12Updated 8 months ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆12Updated 8 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆52Updated 5 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- course design☆22Updated 7 years ago