antmicro / fastvdmaLinks
Antmicro's fast, vendor-neutral DMA IP in Chisel
☆122Updated 2 months ago
Alternatives and similar repositories for fastvdma
Users that are interested in fastvdma are comparing it to the libraries listed below
Sorting:
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆106Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆138Updated 2 weeks ago
- RISC-V Verification Interface☆99Updated 2 months ago
- FuseSoC standard core library☆146Updated 2 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆140Updated 2 years ago
- RISC-V Nox core☆66Updated 2 weeks ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 4 months ago
- PCI express simulation framework for Cocotb☆170Updated 3 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 9 months ago
- A simple DDR3 memory controller☆58Updated 2 years ago
- Labs to learn SpinalHDL☆149Updated last year
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆107Updated last week
- Extensible FPGA control platform☆62Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 7 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆97Updated last month
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆69Updated last year
- A demo system for Ibex including debug support and some peripherals☆73Updated last month
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆64Updated 9 months ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆154Updated last month
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆215Updated 3 weeks ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆64Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆73Updated 2 years ago
- Naive Educational RISC V processor☆85Updated 3 weeks ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆167Updated last week