Alternatives and similar repositories for fastvdma

Users that are interested in fastvdma are comparing it to the libraries listed below

• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 6 months ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆82Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated 2 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆122Updated 4 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆148Updated this week
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 6 months ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆88Updated 4 years ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities
  ☆132Updated this week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated this week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆82Updated 10 months ago
• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆101Updated 7 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆195Updated this week
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆147Updated 2 years ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆220Updated last month
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆53Updated last week
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆73Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 6 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆81Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆227Updated 10 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆164Updated 2 months ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆192Updated 5 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆170Updated 3 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 6 years ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆135Updated 2 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆172Updated 2 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆130Updated 8 months ago