antmicro / fastvdmaLinks
Antmicro's fast, vendor-neutral DMA IP in Chisel
☆125Updated 5 months ago
Alternatives and similar repositories for fastvdma
Users that are interested in fastvdma are comparing it to the libraries listed below
Sorting:
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆115Updated 4 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆142Updated last week
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- FuseSoC standard core library☆147Updated 5 months ago
- RISC-V Verification Interface☆108Updated this week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated last year
- Labs to learn SpinalHDL☆149Updated last year
- A basic SpinalHDL project☆86Updated 2 months ago
- RISC-V Nox core☆68Updated 3 months ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆121Updated this week
- The multi-core cluster of a PULP system.☆108Updated 3 weeks ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 10 months ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 7 months ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆127Updated 6 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆158Updated 3 weeks ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 7 months ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- Yet Another RISC-V Implementation☆98Updated last year
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- ☆27Updated 4 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- A simple DDR3 memory controller☆60Updated 2 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 4 months ago
- OmniXtend cache coherence protocol☆82Updated 4 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆66Updated last year
- Generic Register Interface (contains various adapters)☆130Updated last week