antmicro / fastvdma
Antmicro's fast, vendor-neutral DMA IP in Chisel
☆113Updated 2 months ago
Alternatives and similar repositories for fastvdma:
Users that are interested in fastvdma are comparing it to the libraries listed below
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆65Updated 9 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆82Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆99Updated 3 years ago
- FuseSoC standard core library☆125Updated this week
- PCI express simulation framework for Cocotb☆146Updated last year
- RISC-V Verification Interface☆84Updated 4 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆61Updated 2 years ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- RISC-V System on Chip Template☆156Updated this week
- Announcements related to Verilator☆38Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆156Updated this week
- FPGA reference design for the the Swerv EH1 Core☆69Updated 5 years ago
- ☆41Updated 4 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆72Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆64Updated this week
- SoC based on VexRiscv and ICE40 UP5K☆152Updated 9 months ago
- Control and status register code generator toolchain☆111Updated last month
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆130Updated last month
- Generic Register Interface (contains various adapters)☆103Updated 4 months ago
- The multi-core cluster of a PULP system.☆68Updated last week
- Verilog implementation of a RISC-V core☆108Updated 6 years ago
- ☆76Updated 10 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆138Updated 7 months ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last week
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆134Updated 2 years ago
- Basic RISC-V Test SoC☆109Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆63Updated 2 years ago
- Yet Another RISC-V Implementation☆86Updated 4 months ago
- Fabric generator and CAD tools☆156Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆116Updated 3 weeks ago