Antmicro's fast, vendor-neutral DMA IP in Chisel
☆129Mar 6, 2026Updated 2 weeks ago
Alternatives and similar repositories for fastvdma
Users that are interested in fastvdma are comparing it to the libraries listed below
Sorting:
- Chisel components for FPGA projects☆129Sep 19, 2023Updated 2 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- ☆17Sep 9, 2024Updated last year
- ☆25Aug 7, 2023Updated 2 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago
- eyeriss-chisel3☆41May 2, 2022Updated 3 years ago
- The working draft to split rocket core out from rocket chip☆14Dec 22, 2023Updated 2 years ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 2 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Jan 23, 2020Updated 6 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Sep 17, 2025Updated 6 months ago
- For contributions of Chisel IP to the chisel community.☆71Nov 7, 2024Updated last year
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 11 years ago
- Experiments with fixed function renderers and Chisel HDL☆60Mar 31, 2019Updated 6 years ago
- An out-of-order processor that supports multiple instruction sets.☆21Aug 23, 2022Updated 3 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl☆11Nov 3, 2021Updated 4 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- ☆14Jun 28, 2022Updated 3 years ago
- ☆22Oct 24, 2020Updated 5 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆235Dec 22, 2025Updated 2 months ago
- Hybrid BFS on Xilinx Zynq☆18Jun 9, 2015Updated 10 years ago
- (System)Verilog to Chisel translator☆116May 20, 2022Updated 3 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆245Apr 29, 2024Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆75Nov 15, 2015Updated 10 years ago
- ☆36Apr 20, 2021Updated 4 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆164Jan 25, 2024Updated 2 years ago
- A Heterogeneous GPU Platform for Chipyard SoC☆44Updated this week
- A tiny POWER Open ISA soft processor written in Chisel☆114Feb 13, 2023Updated 3 years ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 3 months ago
- ☆10Apr 8, 2021Updated 4 years ago
- A Scala library for Context-Dependent Environments☆51Apr 25, 2024Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 4 months ago
- HDMI core in Chisel HDL☆53Mar 8, 2024Updated 2 years ago
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 6 months ago
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆20Oct 22, 2025Updated 4 months ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year