PacoReinaCampo / MPSoC-RISCVLinks
Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128
☆13Updated 4 months ago
Alternatives and similar repositories for MPSoC-RISCV
Users that are interested in MPSoC-RISCV are comparing it to the libraries listed below
Sorting:
- NoC based MPSoC☆11Updated 11 years ago
- Network on Chip for MPSoC☆28Updated 4 months ago
- Common SystemVerilog RTL modules for RgGen☆13Updated last month
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆34Updated 4 months ago
- APB Logic☆20Updated this week
- ☆13Updated 7 months ago
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆29Updated 2 weeks ago
- ASIC Design of the openSPARC Floating Point Unit☆14Updated 8 years ago
- Contains commonly used UVM components (agents, environments and tests).☆30Updated 7 years ago
- UVM testbench for verifying the Pulpino SoC☆14Updated 5 years ago
- WISHBONE Interconnect☆11Updated 8 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 9 months ago
- Direct Access Memory for MPSoC☆13Updated 4 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 7 months ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 9 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated 4 months ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Updated 3 years ago
- ☆21Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated last year
- ☆19Updated last month
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 4 years ago
- Design and UVM-TB of RISC -V Microprocessor☆28Updated last year
- UVM resource from github, run simulation use YASAsim flow☆30Updated 5 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago