PacoReinaCampo / MPSoC-RISCVLinks
Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128
☆13Updated 2 weeks ago
Alternatives and similar repositories for MPSoC-RISCV
Users that are interested in MPSoC-RISCV are comparing it to the libraries listed below
Sorting:
- Network on Chip for MPSoC☆28Updated 2 weeks ago
- ☆32Updated this week
- ☆13Updated 9 months ago
- ASIC Design of the openSPARC Floating Point Unit☆15Updated 8 years ago
- APB Logic☆22Updated 2 weeks ago
- UVM testbench for verifying the Pulpino SoC☆14Updated 5 years ago
- Contains commonly used UVM components (agents, environments and tests).☆31Updated 7 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- NoC based MPSoC☆11Updated 11 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated 6 months ago
- Direct Access Memory for MPSoC☆13Updated 2 weeks ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 11 months ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 2 months ago
- ☆19Updated last month
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 10 years ago
- An open source PDK using TIGFET 10nm devices.☆54Updated 2 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated 2 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆20Updated 4 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated 3 weeks ago
- ☆21Updated 5 years ago
- ☆22Updated 6 years ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Updated 3 years ago
- The memory model was leveraged from micron.☆24Updated 7 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆33Updated 4 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆31Updated last week
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated last week