PacoReinaCampo / MPSoC-RISCVLinks
Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128
☆13Updated 3 months ago
Alternatives and similar repositories for MPSoC-RISCV
Users that are interested in MPSoC-RISCV are comparing it to the libraries listed below
Sorting:
- NoC based MPSoC☆11Updated 11 years ago
- Direct Access Memory for MPSoC☆13Updated 3 months ago
- ☆30Updated last week
- Contains commonly used UVM components (agents, environments and tests).☆30Updated 7 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 9 years ago
- Network on Chip for MPSoC☆27Updated 3 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆35Updated 8 months ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆34Updated 3 months ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 2 months ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated last year
- UVM testbench for verifying the Pulpino SoC☆14Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- ☆19Updated 3 weeks ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Updated 6 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Generate UVM testbench framework template files with Python 3☆26Updated 5 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆20Updated 2 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Updated 3 years ago
- Open Source PHY v2☆29Updated last year
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Updated 5 years ago
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- UVM Clock and Reset Agent☆13Updated 8 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated 3 weeks ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated 6 months ago