google / bottlerocketLinks
☆110Updated 7 years ago
Alternatives and similar repositories for bottlerocket
Users that are interested in bottlerocket are comparing it to the libraries listed below
Sorting:
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆175Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuits☆123Updated 2 years ago
- Provides various testers for chisel users☆100Updated 3 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- Chisel components for FPGA projects☆128Updated 2 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- ☆87Updated last week
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Updated 6 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆60Updated 2 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆153Updated 3 weeks ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆106Updated 7 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- Chisel Learning Journey☆111Updated 2 years ago
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆170Updated 5 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆73Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆184Updated 8 months ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 6 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆75Updated 10 years ago
- Chisel/Firrtl execution engine☆155Updated last year
- Connectal is a framework for software-driven hardware development.☆176Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆129Updated 6 years ago
- A template for building new projects/platforms using the BOOM core.☆25Updated 7 years ago
- ☆88Updated 3 years ago
- An Open-Source Design and Verification Environment for RISC-V☆86Updated 4 years ago
- RISC-V Torture Test☆212Updated last year