google / bottlerocketLinks
☆110Updated 7 years ago
Alternatives and similar repositories for bottlerocket
Users that are interested in bottlerocket are comparing it to the libraries listed below
Sorting:
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- Provides various testers for chisel users☆100Updated 2 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- ☆87Updated last week
- Chisel components for FPGA projects☆127Updated 2 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆179Updated 6 months ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆218Updated 5 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆174Updated 5 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆165Updated 5 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Basic floating-point components for RISC-V processors☆67Updated 5 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆149Updated 2 weeks ago
- Yet Another RISC-V Implementation☆99Updated last year
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆59Updated 2 years ago
- Main page☆128Updated 5 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆105Updated 7 years ago
- RISC-V Torture Test☆202Updated last year
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆241Updated last year
- Chisel Learning Journey☆111Updated 2 years ago
- OmniXtend cache coherence protocol☆82Updated 5 months ago
- Chisel/Firrtl execution engine☆153Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 6 years ago
- ☆50Updated 2 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Setup scripts and files needed to compile CoreMark on RISC-V☆71Updated last year
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 6 years ago