google / bottlerocketLinks
☆109Updated 6 years ago
Alternatives and similar repositories for bottlerocket
Users that are interested in bottlerocket are comparing it to the libraries listed below
Sorting:
- Provides various testers for chisel users☆99Updated 2 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Provides dot visualizations of chisel/firrtl circuits☆121Updated 2 years ago
- Chisel components for FPGA projects☆126Updated 2 years ago
- ☆85Updated 4 months ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆57Updated 2 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆163Updated 5 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 5 months ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆215Updated 5 years ago
- Chisel Learning Journey☆110Updated 2 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Chisel/Firrtl execution engine☆153Updated last year
- A Library of Chisel3 Tools for Digital Signal Processing☆238Updated last year
- OpenSoC Fabric - A Network-On-Chip Generator☆172Updated 5 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆148Updated 2 months ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- Main page☆128Updated 5 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆155Updated last year
- Yet Another RISC-V Implementation☆98Updated last year
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆103Updated 6 years ago
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year
- RISC-V Torture Test☆200Updated last year
- ☆88Updated 2 years ago
- OmniXtend cache coherence protocol☆82Updated 4 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago