freecores / tiny_aesLinks
AES
☆14Updated 2 years ago
Alternatives and similar repositories for tiny_aes
Users that are interested in tiny_aes are comparing it to the libraries listed below
Sorting:
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- DSP WishBone Compatible Cores☆14Updated 11 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆18Updated 7 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- Generic AXI master stub☆19Updated 11 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆17Updated 6 years ago
- A CIC filter implemented in Verilog☆22Updated 9 years ago
- Advanced Debug Interface☆15Updated 6 months ago
- ☆33Updated 2 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated 2 months ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Updated 4 months ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 6 months ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆18Updated 11 months ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆28Updated 9 years ago
- ☆17Updated 9 months ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 6 months ago
- ☆16Updated 6 years ago
- Pipelined FFT/IFFT 64 points processor☆12Updated 11 years ago
- Network on Chip for MPSoC☆26Updated 2 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆20Updated 3 years ago
- ☆18Updated 4 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆28Updated last month
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆11Updated 5 years ago
- RISC-V soft-core PEs for TaPaSCo☆22Updated last year
- ☆30Updated 2 weeks ago