Alternatives and similar repositories for tagged_security_riscv

Users that are interested in tagged_security_riscv are comparing it to the libraries listed below

• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 7 years ago
• hackdac / hackdac_2018_beta
  The SoC used for the beta phase of Hack@DAC 2018.
  ☆17Updated 5 years ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 4 years ago
• HWSec-UNC / Sylvia
  ☆18Updated 4 months ago
• ekiwi / rfuzz
  rfuzz: coverage-directed fuzzing for RTL research platform
  ☆112Updated 3 years ago
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆65Updated 6 years ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆17Updated 4 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆47Updated 2 weeks ago
• comsec-group / cellift-meta
  All the tools you need to reproduce the CellIFT paper experiments
  ☆22Updated 8 months ago
• Chair-for-Security-Engineering / SILVER
  SILVER - Statistical Independence and Leakage Verification
  ☆14Updated 4 months ago
• comsec-group / encarsia
  ☆24Updated 6 months ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆78Updated last year
• impedimentToProgress / A2
  ☆14Updated 8 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆27Updated 4 months ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated last month
• compsec-snu / specdoctor
  ☆25Updated 2 years ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆22Updated 3 years ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆90Updated this week
• daniellustig / coatcheck
  COATCheck
  ☆13Updated 6 years ago
• ekiwi / simulator-independent-coverage
  Project Repo for the Simulator Independent Coverage Research
  ☆21Updated 2 years ago
• masc-ucsc / fluid
  Fluid Pipelines
  ☆11Updated 7 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆36Updated 3 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆58Updated last week
• compsec-snu / difuzz-rtl
  ☆95Updated last year
• cwfletcher / stt
  ☆35Updated 4 years ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆69Updated this week
• skmuduli92 / HyperFuzzer
  ☆16Updated 4 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆73Updated 7 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 4 years ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆113Updated this week