zzyppo / tagged_security_riscv

Related projects ⓘ

Alternatives and complementary repositories for tagged_security_riscv

• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆28Updated 6 years ago
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆14Updated 3 weeks ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆29Updated last month
• hackdac / hackdac_2018_beta
  The SoC used for the beta phase of Hack@DAC 2018.
  ☆17Updated 4 years ago
• Chair-for-Security-Engineering / SILVER
  SILVER - Statistical Independence and Leakage Verification
  ☆12Updated last year
• ekiwi / rfuzz
  rfuzz: coverage-directed fuzzing for RTL research platform
  ☆98Updated 2 years ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆20Updated 4 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆42Updated last month
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆61Updated 5 years ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆20Updated this week
• ekiwi / simulator-independent-coverage
  Project Repo for the Simulator Independent Coverage Research
  ☆16Updated last year
• RPTU-EIS / upec-boom-verification-suite
  This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…
  ☆15Updated last year
• efeslab / hardware-bugbase
  ☆16Updated 5 months ago
• compsec-snu / difuzz-rtl
  ☆74Updated 5 months ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆22Updated last month
• ilebedev / sanctum
  The MIT Sanctum processor top-level project
  ☆28Updated 4 years ago
• riscv-admin / security
  RISC-V Security HC admin repo
  ☆15Updated last month
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆54Updated 3 months ago
• googleinterns / hw-fuzzing
  ☆78Updated last year
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆75Updated this week
• compsec-snu / specdoctor
  ☆19Updated last year
• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆58Updated 4 years ago
• masc-ucsc / fluid
  Fluid Pipelines
  ☆11Updated 6 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆29Updated 2 years ago
• cwfletcher / stt
  ☆34Updated 3 years ago
• vmarribas / VerMFi
  VerMFi: Verification tool for Masked implementations and Fault injection. Set of tools to evaluate resistance of secure hardware against …
  ☆17Updated 5 years ago
• TsaiAnson / verif
  ☆11Updated 3 years ago
• newaetech / sonata-pcb
  Design files and associated documentation for Sonata PCB, part of the Sunburst Project
  ☆13Updated 5 months ago
• bu-icsg / PHMon
  This repository contains the hardware, software, and OS support for the Programmable Hardware Monitor (PHMon).
  ☆25Updated 4 years ago
• riscv-admin / iopmp
  Group administration repository for Tech: IOPMP Task Group
  ☆13Updated 2 weeks ago