Alternatives and similar repositories for verif

Users that are interested in verif are comparing it to the libraries listed below

• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 4 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 4 months ago
• masc-ucsc / fluid
  Fluid Pipelines
  ☆11Updated 7 years ago
• ucb-bar / fixedpoint
  Chisel Fixed-Point Arithmetic Library
  ☆17Updated last month
• chick / visualizer
  Provides dot visualizations of chisel/firrtl circuites
  ☆13Updated 6 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 3 years ago
• ucb-art / fft
  ☆20Updated 5 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆33Updated 3 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆34Updated 2 years ago
• euphoric-hardware / simcommand
  SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.
  ☆14Updated 2 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• IBM / esp-chisel-accelerators
  Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
  ☆24Updated 6 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 3 years ago
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆13Updated 10 years ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆32Updated 2 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• tdb-alcorn / chisel-formal
  ☆24Updated 4 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 7 months ago
• StanfordAHA / doc
  Papers, Posters, Presentations, Documentation...
  ☆19Updated 2 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆38Updated 3 months ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆57Updated 3 weeks ago
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆27Updated 2 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆98Updated last year
• esa-tu-darmstadt / SCAIE-V-2.0
  ☆23Updated last week
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆51Updated 5 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆14Updated last year
• inferablejump / bagpype
  ☆15Updated last month
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year