Alternatives and similar repositories for zscale

Users that are interested in zscale are comparing it to the libraries listed below

• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆96Updated 11 months ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆102Updated 6 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆183Updated 8 months ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 9 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆75Updated 6 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 5 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆57Updated 5 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆84Updated 5 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆64Updated 6 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆145Updated last week
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆58Updated 8 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆59Updated 9 months ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 5 months ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆172Updated last year
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆124Updated 9 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆120Updated 11 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 2 months ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆88Updated 6 years ago
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆163Updated 2 months ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago