ucb-bar / zscaleLinks
Z-scale Microarchitectural Implementation of RV32 ISA
☆55Updated 8 years ago
Alternatives and similar repositories for zscale
Users that are interested in zscale are comparing it to the libraries listed below
Sorting:
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 8 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆74Updated 6 years ago
- Yet Another RISC-V Implementation☆93Updated 9 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- ☆63Updated 6 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- A utility for Composing FPGA designs from Peripherals☆179Updated 6 months ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆74Updated 6 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Core description files for FuseSoC☆124Updated 4 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆101Updated 6 years ago
- Project X-Ray Database: XC7 Series☆69Updated 3 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- OmniXtend cache coherence protocol☆82Updated last week
- Naive Educational RISC V processor☆84Updated 2 weeks ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 7 years ago
- Open Processor Architecture☆26Updated 9 years ago
- FuseSoC standard core library☆143Updated 3 weeks ago
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆123Updated 8 years ago
- Spen's Official OpenOCD Mirror☆50Updated 3 months ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆40Updated 9 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated 3 weeks ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆96Updated 3 years ago