TYOD-SOC / RISCV-AcceleratorLinks
☆36Updated 6 years ago
Alternatives and similar repositories for RISCV-Accelerator
Users that are interested in RISCV-Accelerator are comparing it to the libraries listed below
Sorting:
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- Implement a bitonic sorting network on FPGA☆46Updated 3 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Updated 9 years ago
- ☆64Updated 2 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆52Updated 2 years ago
- ☆42Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆65Updated last year
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆109Updated 2 years ago
- ☆86Updated this week
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 3 years ago
- ☆53Updated 6 years ago
- Pure digital components of a UCIe controller☆69Updated this week
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- ☆38Updated last year
- GPGPU supporting RISCV-V, developed with verilog HDL☆110Updated 6 months ago
- SpinalHDL-tutorial based on Jupyter Notebook☆139Updated last year
- ☆18Updated 2 years ago
- ☆66Updated 3 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆79Updated 7 years ago
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- HYF's high quality verilog codes☆15Updated 8 months ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- ☆62Updated 3 years ago
- systemc建模相关☆27Updated 11 years ago
- ☆29Updated 5 years ago
- ☆31Updated 6 months ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆29Updated last week
- ☆68Updated 9 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆78Updated 2 years ago
- ☆22Updated 2 years ago