☆37Nov 11, 2018Updated 7 years ago
Alternatives and similar repositories for RISCV-Accelerator
Users that are interested in RISCV-Accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Apr 6, 2020Updated 6 years ago
- The 'missing header' for Chisel☆23Feb 5, 2026Updated 2 months ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆15Sep 5, 2019Updated 6 years ago
- eyeriss-chisel3☆41May 2, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆16Dec 4, 2021Updated 4 years ago
- RADIX-4 SRT division☆12Oct 31, 2019Updated 6 years ago
- scratchip is a framework that can help to build your Chisel and Verilog/Systemverilog project easier.☆15Nov 2, 2022Updated 3 years ago
- [DATE'2025, TCAD'2025] Terafly : A Multi-Node FPGA Based Accelerator Design for Efficient Cooperative Inference in LLMs☆36Nov 13, 2025Updated 5 months ago
- WISHBONE DMA/Bridge IP Core☆18Jul 17, 2014Updated 11 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆223Jan 23, 2020Updated 6 years ago
- ☆16Apr 21, 2019Updated 7 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 8 months ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆22Oct 24, 2020Updated 5 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- ☆12Sep 18, 2024Updated last year
- Custom Coprocessor Interface for VexRiscv☆10Sep 19, 2018Updated 7 years ago
- 🎞️ NoC router in Verilog with FIFO☆16Sep 1, 2022Updated 3 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- ☆10Oct 8, 2021Updated 4 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆37Oct 23, 2025Updated 6 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Chisel Things for OFDM☆33Jul 1, 2020Updated 5 years ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 8 months ago
- A Zero Cost Abstruction of FSM(Finite State Machine) circuits based on chisel3.☆13Oct 8, 2021Updated 4 years ago
- AHB Bus lite v3.0☆17Aug 7, 2019Updated 6 years ago
- Introduction to Computer Systems (II), Spring 2021☆52Jul 3, 2021Updated 4 years ago
- Ventus GPGPU ISA Simulator Based on Spike☆51Updated this week
- Simple MIDAS Examples☆12Nov 25, 2018Updated 7 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Aug 8, 2017Updated 8 years ago
- Devotes to open source FPGA☆28May 9, 2020Updated 5 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl☆11Nov 3, 2021Updated 4 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Apr 19, 2026Updated 2 weeks ago
- Helper scripts used to clone RISC-V related git repos inside China.☆16Sep 17, 2020Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago
- Testbenches for HDL projects☆23Apr 20, 2026Updated 2 weeks ago