Alternatives and similar repositories for RISCV-Accelerator:

Users that are interested in RISCV-Accelerator are comparing it to the libraries listed below

• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆38Updated last year
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• yaozhaosh / e200_opensource
  The Ultra-Low Power RISC Core
  ☆15Updated 4 years ago
• zhaishaomin / ring_network-based-multicore-
  多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency
  ☆23Updated 8 years ago
• pulp-platform / fpu
  ☆43Updated 6 years ago
• OSCPU / ysyxSoC
  ☆85Updated 2 months ago
• OpenXiangShan / XS-Verilog-Library
  ☆41Updated 2 years ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆61Updated 2 weeks ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆61Updated last year
• wangeddie67 / ESYSim
  ☆35Updated 10 months ago
• RicardoNid / ChainsawOld
  ☆23Updated 2 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆42Updated 4 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆67Updated 5 months ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆103Updated 2 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆133Updated 10 months ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• ansonn / esl_systemc
  systemc建模相关
  ☆27Updated 10 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 9 months ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆58Updated 3 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆58Updated 3 years ago
• lingscale / cc01
  ☆31Updated last month
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆39Updated 2 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆132Updated 2 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆37Updated 2 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆55Updated last month
• sunyata000 / AMY_MCU
  A MCU implementation based PODES-M0O
  ☆18Updated 5 years ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆61Updated 2 years ago