Chlorophytus / broccoliLinks
A soft multimedia/graphics processor prototype in Chisel 3
☆11Updated 2 years ago
Alternatives and similar repositories for broccoli
Users that are interested in broccoli are comparing it to the libraries listed below
Sorting:
- Wrapper for ETH Ariane Core☆21Updated 3 months ago
- A coverage library for Chisel designs☆11Updated 5 years ago
- Block-diagram style digital logic visualizer☆23Updated 10 years ago
- RTL blocks compatible with the Rocket Chip Generator☆16Updated 8 months ago
- ☆13Updated 4 years ago
- RISC-V GPGPU☆36Updated 5 years ago
- Useful utilities for BAR projects☆32Updated last year
- Wrappers for open source FPU hardware implementations.☆35Updated 2 weeks ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 3 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆31Updated 4 years ago
- ☆20Updated 4 years ago
- DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language☆92Updated this week
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- BFM Tester for Chisel HDL☆14Updated 4 years ago
- Chisel Cheatsheet☆34Updated 2 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- The home of the Chisel3 website☆21Updated last year
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆14Updated 2 weeks ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- Chisel/Firrtl execution engine☆153Updated last year
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Updated 7 years ago
- chipyard in mill :P☆77Updated 2 years ago
- A Rocket-based RISC-V superscalar in-order core☆36Updated 2 months ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Updated 6 years ago
- ☆22Updated 5 years ago