Chlorophytus / broccoliLinks
A soft multimedia/graphics processor prototype in Chisel 3
☆11Updated 2 years ago
Alternatives and similar repositories for broccoli
Users that are interested in broccoli are comparing it to the libraries listed below
Sorting:
- Wrapper for ETH Ariane Core☆21Updated 2 months ago
- A coverage library for Chisel designs☆11Updated 5 years ago
- Block-diagram style digital logic visualizer☆23Updated 10 years ago
- ☆20Updated 4 years ago
- Useful utilities for BAR projects☆32Updated last year
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆31Updated 4 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- ☆13Updated 4 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- RISC-V GPGPU☆35Updated 5 years ago
- DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language☆92Updated this week
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- RTL blocks compatible with the Rocket Chip Generator☆16Updated 7 months ago
- Chisel/Firrtl execution engine☆153Updated last year
- BFM Tester for Chisel HDL☆14Updated 3 years ago
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December…☆23Updated 4 years ago
- ☆57Updated 3 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆49Updated 2 years ago
- Network components (NIC, Switch) for FireBox☆19Updated last year
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Updated 11 months ago
- The PE for the second generation CGRA (garnet).☆17Updated 6 months ago
- HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…☆21Updated 9 years ago
- A Rocket-based RISC-V superscalar in-order core☆36Updated last month
- Benchmarks for Yosys development☆24Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 5 years ago
- The home of the Chisel3 website☆21Updated last year
- Wrappers for open source FPU hardware implementations.☆35Updated last year