Alternatives and similar repositories for broccoli

Users that are interested in broccoli are comparing it to the libraries listed below

• ucb-bar / cva6-wrapper
  Wrapper for ETH Ariane Core
  ☆21Updated 2 months ago
• freechipsproject / chisel-coverage
  A coverage library for Chisel designs
  ☆11Updated 5 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 3 years ago
• ducky64 / chisualizer
  Block-diagram style digital logic visualizer
  ☆23Updated 10 years ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆35Updated 5 years ago
• ucb-bar / chisel-awl
  ☆13Updated 4 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆34Updated last year
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated last month
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆32Updated last year
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆91Updated last week
• x-epic / EpicFV
  ☆20Updated 4 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆31Updated 4 years ago
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆16Updated 7 months ago
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆13Updated 10 years ago
• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 3 years ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated last year
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆34Updated 2 years ago
• franzflasch / leiwand_rv32
  RISC-V RV32I CPU written in verilog
  ☆10Updated 5 years ago
• ucb-bar / esp-isa-sim
  Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
  ☆17Updated 2 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆35Updated 3 weeks ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• firesim / icenet
  Network components (NIC, Switch) for FireBox
  ☆19Updated last year
• SymbioticEDA / getting-started-FV
  ☆18Updated 5 years ago
• IBM / esp-chisel-accelerators
  Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
  ☆24Updated 5 years ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆39Updated last year
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆53Updated 5 years ago
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆22Updated 9 months ago
• sequencer / arithmetic
  ☆33Updated 7 months ago