Chlorophytus / broccoli
A soft multimedia/graphics processor prototype in Chisel 3
☆11Updated last year
Alternatives and similar repositories for broccoli:
Users that are interested in broccoli are comparing it to the libraries listed below
- Wrapper for ETH Ariane Core☆19Updated 6 months ago
- Useful utilities for BAR projects☆31Updated last year
- RTL blocks compatible with the Rocket Chip Generator☆14Updated 7 months ago
- An example of on-boarding a PIO block in with duh and wake☆12Updated 4 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- ☆10Updated 5 years ago
- This repo includes XiangShan's function units☆18Updated this week
- an experiment to run plugin in firtool pipeline☆9Updated last year
- A Rocket-based RISC-V superscalar in-order core☆29Updated 2 weeks ago
- An RTL generator for a last-level shared inclusive TileLink cache controller☆16Updated last month
- Block-diagram style digital logic visualizer☆23Updated 9 years ago
- A coverage library for Chisel designs☆11Updated 4 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- RISC-V GPGPU☆34Updated 4 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated last week
- DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language☆84Updated this week
- Hardfloat using chisel3☆17Updated 4 years ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆16Updated 2 months ago
- The home of the Chisel3 website☆20Updated 8 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated last week
- ☆13Updated 4 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆28Updated 3 years ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆71Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- firrtlator is a FIRRTL C++ library☆21Updated 8 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆15Updated 5 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago