eanchlia / NN_Network_On_Chip
Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to interface four instances of neural engine with AHB bus to create NOC.
☆11Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for NN_Network_On_Chip
- CNN accelerator using NoC architecture☆15Updated 5 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆13Updated 10 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- ☆16Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆18Updated 7 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆10Updated 4 years ago
- DMA core compatible with AHB3-Lite☆10Updated 5 years ago
- verification of simple axi-based cache☆17Updated 5 years ago
- Direct Access Memory for MPSoC☆12Updated 3 weeks ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆12Updated 9 years ago
- Design and UVM-TB of RISC -V Microprocessor☆13Updated 4 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆12Updated 9 months ago
- ☆20Updated 5 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆14Updated 4 years ago
- ☆16Updated 2 years ago
- CORE-V MCU UVM Environment and Test Bench☆17Updated 4 months ago
- ☆25Updated 4 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆17Updated 5 years ago
- ☆22Updated 5 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 3 years ago
- Network on Chip for MPSoC☆25Updated 3 weeks ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆31Updated last year
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- EE577b-Course-Project☆15Updated 4 years ago
- NoC based MPSoC☆10Updated 10 years ago
- 位宽和深度可定制的异步FIFO☆12Updated 5 months ago
- ☆9Updated 4 years ago
- UVM testbench for verifying the Pulpino SoC☆14Updated 4 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆10Updated 3 weeks ago