Alternatives and similar repositories for NN_Network_On_Chip:

Users that are interested in NN_Network_On_Chip are comparing it to the libraries listed below

• frobino / Nostrum-SystemC-simulator
  SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).
  ☆14Updated 10 years ago
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆16Updated 6 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆11Updated 4 years ago
• KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip
  EE577b-Course-Project
  ☆16Updated 4 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 5 years ago
• yuhsaun-t / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆19Updated 7 years ago
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆12Updated 9 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 5 years ago
• hyoukjun / microswitch-noc
  ☆25Updated 5 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆14Updated 8 months ago
• freecores / an-fpga-implementation-of-low-latency-noc-based-mpsoc
  NoC based MPSoC
  ☆10Updated 10 years ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago
• pulp-platform / hwpe-stream
  IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
  ☆19Updated 2 weeks ago
• nguyenquanicd / AllArbiterRTLCode
  RTL code of some arbitration algorithm
  ☆13Updated 5 years ago
• open-dv / dma_axi
  ☆16Updated 5 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆19Updated 7 months ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆14Updated last year
• muneebullashariff / pulpino_soc_uvm_testbench
  UVM testbench for verifying the Pulpino SoC
  ☆13Updated 4 years ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆14Updated 4 years ago
• ljgibbslf / basic_cache_core
  ☆25Updated 4 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆27Updated this week
• wanderingnail / AXI_DMA
  ☆19Updated 2 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 3 years ago
• vinodsake / Last-Level-Cache-Simulator
  ☆12Updated 7 years ago
• JoseIuri / UVM_Python_UVMC
  This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…
  ☆15Updated 5 years ago
• pulp-platform / axi_spi_master
  ☆20Updated 5 years ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆13Updated 7 years ago
• PacoReinaCampo / MPSoC-NoC
  Network on Chip for MPSoC
  ☆26Updated 2 weeks ago
• PacoReinaCampo / MPSoC-DMA
  Direct Access Memory for MPSoC
  ☆12Updated 2 weeks ago
• gilani / fpfma
  Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)
  ☆18Updated 11 years ago