TUM-LIS / lisnocLinks
LIS Network-on-Chip Implementation
☆30Updated 8 years ago
Alternatives and similar repositories for lisnoc
Users that are interested in lisnoc are comparing it to the libraries listed below
Sorting:
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- ☆30Updated this week
- ☆16Updated 2 weeks ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- ☆20Updated 5 years ago
- Platform Level Interrupt Controller☆41Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- AXI X-Bar☆19Updated 5 years ago
- SoCRocket - Core Repository☆37Updated 8 years ago
- DUTH RISC-V Microprocessor☆20Updated 7 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆32Updated last month
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Network on Chip for MPSoC☆26Updated last month
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆32Updated 6 months ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 5 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆29Updated last month
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- YosysHQ SVA AXI Properties☆41Updated 2 years ago
- RISC-V soft-core PEs for TaPaSCo☆22Updated last year
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated last month
- PCI Express controller model☆58Updated 2 years ago
- Advanced Debug Interface☆15Updated 5 months ago
- General Purpose AXI Direct Memory Access☆53Updated last year