TUM-LIS / lisnocLinks
LIS Network-on-Chip Implementation
☆34Updated 9 years ago
Alternatives and similar repositories for lisnoc
Users that are interested in lisnoc are comparing it to the libraries listed below
Sorting:
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 months ago
- ☆22Updated 5 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated last year
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- ☆33Updated 2 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- SoCRocket - Core Repository☆38Updated 8 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 months ago
- Network on Chip for MPSoC☆28Updated 2 weeks ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- ☆31Updated 5 years ago
- Advanced Debug Interface☆14Updated last year
- ☆20Updated last month
- Platform Level Interrupt Controller☆44Updated last year
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆19Updated last year
- JTAG DPI module for SystemVerilog RTL simulations☆32Updated 10 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- AXI X-Bar☆19Updated 5 years ago
- DUTH RISC-V Microprocessor☆23Updated last year
- AXI3 Bus Functional Models (Initiator & Target)☆30Updated 3 years ago
- ASIC Design of the openSPARC Floating Point Unit☆15Updated 8 years ago
- APB Logic☆23Updated 3 weeks ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 9 years ago
- ☆74Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 5 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 4 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Updated 5 years ago