Alternatives and similar repositories for cvfpu

Users that are interested in cvfpu are comparing it to the libraries listed below

• Aquaticfuller / OpenExSys_NoC
  OpenExSys_NoC a mesh-based network on chip IP.
  ☆20Updated 2 years ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆22Updated 6 years ago
• Purdue-SoCET / atalla
  Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.
  ☆23Updated this week
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• pulp-platform / axi_llc
  ☆33Updated 2 months ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• CMU-SAFARI / MIG-7-PHY-DDR3-Controller
  A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.
  ☆11Updated 4 years ago
• sld-columbia / esp-caches
  SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
  ☆18Updated 11 months ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆28Updated 2 months ago
• hyoukjun / microswitch-noc
  ☆29Updated 6 years ago
• atfox272 / AXI4-Interconnect
  RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…
  ☆23Updated 10 months ago
• yhinai / TensorGPGPU
  RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…
  ☆19Updated 9 months ago
• chipsalliance / aib-protocols
  ☆29Updated last year
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆18Updated 5 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆33Updated last year
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆39Updated 4 years ago
• pulp-platform / quadrilatero
  matrix-coprocessor for RISC-V
  ☆29Updated last month
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆31Updated last month
• pulp-platform / ace
  ☆20Updated last month
• liang-aquarius / ca_model
  A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…
  ☆17Updated 6 years ago
• pulp-platform / axi-io-pmp
  Input / Output Physical Memory Protection Unit for RISC-V
  ☆15Updated 2 years ago
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆34Updated 8 years ago
• pulp-platform / hier-icache
  ☆14Updated 11 months ago
• Aquaticfuller / OpenExSys_CoherentCache
  OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.
  ☆20Updated 10 months ago
• Nikola2444 / RISC-V-vector-processor
  ☆15Updated 3 years ago
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆17Updated 2 years ago
• pulp-platform / apb
  APB Logic
  ☆23Updated last week
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆30Updated 3 years ago
• StanfordVLSI / FP-Gen
  FPU Generator
  ☆20Updated 4 years ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆29Updated 4 years ago