pulp-platform / cvfpuLinks
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
☆17Updated last month
Alternatives and similar repositories for cvfpu
Users that are interested in cvfpu are comparing it to the libraries listed below
Sorting:
- The official NaplesPU hardware code repository☆18Updated 6 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆29Updated 5 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆22Updated last year
- ☆29Updated last month
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆29Updated this week
- OpenExSys_NoC a mesh-based network on chip IP.☆16Updated last year
- ☆13Updated 7 months ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆15Updated 6 months ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated 6 months ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- ☆10Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 11 months ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated 3 weeks ago
- ☆13Updated this week
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆35Updated 9 months ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Updated 6 years ago
- Original test vector of RISC-V Vector Extension☆14Updated 4 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 11 years ago
- ☆53Updated 6 years ago
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- ☆21Updated 5 years ago
- ☆19Updated 3 weeks ago
- RISC-V IOMMU in verilog☆19Updated 3 years ago