Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
☆23Aug 29, 2026Updated this week
Alternatives and similar repositories for cvfpu
Users that are interested in cvfpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Aug 19, 2026Updated last week
- Open source high performance IEEE-754 floating unit☆99Feb 26, 2024Updated 2 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆13Aug 26, 2023Updated 3 years ago
- ☆25Apr 17, 2026Updated 4 months ago
- An energy-efficient RISC-V floating-point compute cluster.☆147Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆17Sep 21, 2025Updated 11 months ago
- ☆12Sep 18, 2024Updated last year
- ☆36Updated this week
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆167Updated this week
- Contract-Aware RTL Code Generation Agents with Temporal Tracing, Slicing and Formal Verification☆24Jan 28, 2026Updated 7 months ago
- FPGA acceleration of arbitrary precision floating point computations.☆41May 17, 2022Updated 4 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆21Sep 2, 2023Updated 2 years ago
- Network components (NIC, Switch) for FireBox☆19Oct 27, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆30Updated this week
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆11Dec 29, 2021Updated 4 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 7 years ago
- Open-source non-blocking L2 cache☆65Updated this week
- AHB3-Lite to Wishbone Bridge☆13Mar 26, 2019Updated 7 years ago
- 将 Verilog 设计规范、流水线模式与 FPGA 优化笔记结构化为可查询的本地知识库,供本地智能代理或脚本检索并返回带出处的实现建议与示例代码。☆25May 23, 2026Updated 3 months ago
- RISC-V fast interrupt controller☆35Aug 6, 2026Updated 3 weeks ago
- GEMM and GEMM-Ops accelerator for PULP systems☆115Aug 5, 2026Updated 3 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 11 years ago
- matrix-coprocessor for RISC-V☆37Feb 27, 2026Updated 6 months ago
- A small DNN library for RISC-V, using RISC-V Vector and Matrix extensions☆11Mar 13, 2025Updated last year
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Slides of Dr Sparsh Mittal on "Computer Architecture for AI" (aka Hardware Architecture for Deep Learning) Course☆18Apr 20, 2026Updated 4 months ago
- ☆15Jun 26, 2026Updated 2 months ago
- A heterogeneous accelerator-centric compute cluster☆56Updated this week
- ☆31Aug 8, 2020Updated 6 years ago
- ☆42Dec 8, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Chisel implementation of Neural Processing Unit for System on the Chip☆35Aug 21, 2026Updated last week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆235Updated this week
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆34May 17, 2026Updated 3 months ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT☆21Updated this week
- ☆19Jul 1, 2024Updated 2 years ago
- The Unified TileLink Memory Subsystem Tester for XiangShan☆15Updated this week