ThalesGroup / cva6-softcore-contestLinks
CVA6 softcore contest
☆21Updated last month
Alternatives and similar repositories for cva6-softcore-contest
Users that are interested in cva6-softcore-contest are comparing it to the libraries listed below
Sorting:
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- ☆14Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated last year
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆37Updated 3 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆33Updated 2 weeks ago
- Advanced Architecture Labs with CVA6☆71Updated last year
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆75Updated 4 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆64Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- BlackParrot on Zynq☆47Updated last week
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆19Updated 2 months ago
- System Verilog BootCamp☆25Updated 3 years ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆39Updated 5 months ago
- ☆12Updated 4 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆38Updated 3 months ago
- Design and UVM-TB of RISC -V Microprocessor☆32Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Updated last month
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆53Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated last week
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Updated 8 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- ☆33Updated last month
- Two Level Cache Controller implementation in Verilog HDL☆53Updated 5 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated 3 weeks ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆13Updated last month
- CORE-V MCU UVM Environment and Test Bench☆25Updated last year