Alternatives and similar repositories for atalla

Users that are interested in atalla are comparing it to the libraries listed below

• yhinai / TensorGPGPU
  RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…
  ☆18Updated 7 months ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆20Updated 6 years ago
• bsc-loca / mmu
  ☆13Updated 7 months ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆32Updated last year
• CMU-SAFARI / MIG-7-PHY-DDR3-Controller
  A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.
  ☆11Updated 4 years ago
• pulp-platform / ace
  ☆20Updated this week
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆17Updated last year
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• pulp-platform / hier-icache
  ☆14Updated 9 months ago
• Aquaticfuller / OpenExSys_CoherentCache
  OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.
  ☆18Updated 8 months ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆29Updated last week
• avikram2 / RISCVPipelinedProcessor
  Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…
  ☆14Updated 2 years ago
• msyksphinz-self / riscv-vector-tests
  Original test vector of RISC-V Vector Extension
  ☆14Updated 4 years ago
• jiayi-wang98 / lpddr4_memory_controller
  ☆10Updated 3 years ago
• hyoukjun / microswitch-noc
  ☆28Updated 6 years ago
• pulp-platform / axi_llc
  ☆32Updated 3 weeks ago
• Aquaticfuller / OpenExSys_NoC
  OpenExSys_NoC a mesh-based network on chip IP.
  ☆18Updated 2 years ago
• pulp-platform / quadrilatero
  matrix-coprocessor for RISC-V
  ☆25Updated this week
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆31Updated last year
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆38Updated 4 years ago
• ucb-bar / radiance
  A Heterogeneous GPU Platform for Chipyard SoC
  ☆40Updated last week
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆26Updated last month
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• sld-columbia / esp-caches
  SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
  ☆17Updated 9 months ago
• pulp-platform / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆18Updated last month
• lycfly / EasyNPU
  A small Neural Network Processor for Edge devices.
  ☆14Updated 3 years ago
• liang-aquarius / ca_model
  A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…
  ☆16Updated 6 years ago
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆25Updated 3 months ago
• nguyenquanicd / AllArbiterRTLCode
  RTL code of some arbitration algorithm
  ☆15Updated 6 years ago
• ved-rivos / iommu-rtl
  RISC-V IOMMU in verilog
  ☆20Updated 3 years ago