Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.
☆29Oct 13, 2026Updated this week
Alternatives and similar repositories for atalla
Users that are interested in atalla are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆22Apr 12, 2026Updated 6 months ago
- RISC-V SIMD Superscalar Dual-Issue Processor☆31Apr 24, 2025Updated last year
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆25Apr 25, 2025Updated last year
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆26Nov 9, 2025Updated 11 months ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆19Oct 2, 2026Updated 2 weeks ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆21Jan 13, 2026Updated 9 months ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆26Aug 29, 2026Updated last month
- Formal Verification of RISC V IM Processor☆12Mar 27, 2022Updated 4 years ago
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- This is a brand new implement of GPGPU called Koala GPU which will be compatible with NV GPU micro architecture starting from fermi. It s…☆19May 31, 2026Updated 4 months ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- ☆22Sep 26, 2025Updated last year
- Artifact for "DX100: A Programmable Data Access Accelerator for Indirection (ISCA 2025)" paper☆20Nov 6, 2025Updated 11 months ago
- Design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit Version 1 in TSMC 16nm☆23Sep 27, 2026Updated 2 weeks ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 11 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Feb 17, 2022Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆34Jun 12, 2023Updated 3 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- CORE-V MCU UVM Environment and Test Bench☆29Jul 19, 2024Updated 2 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆62Jan 20, 2026Updated 8 months ago
- Hardware acceleration for transformer attention mechanisms on NVIDIA Deep Learning Accelerator (NVDLA), enabling efficient inference of…☆20Mar 30, 2025Updated last year
- AES☆16Oct 4, 2022Updated 4 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆19Oct 5, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆45May 5, 2023Updated 3 years ago
- RTL implementation of a ray-tracing GPU☆17Dec 18, 2012Updated 13 years ago
- ☆15Apr 28, 2026Updated 5 months ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆36Jul 17, 2025Updated last year
- ☆10Dec 15, 2023Updated 2 years ago
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Updated this week
- ☆93Apr 22, 2025Updated last year
- A Customized ASIC framework for Retro Stuff☆36Updated this week
- Accelerator RTL inspired by VEGETA [HPCA'23] and MicroScopiQ [ISCA'25]☆16Nov 11, 2025Updated 11 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Programming and Assignment Material for ECE 695☆18Apr 23, 2021Updated 5 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆45Oct 10, 2026Updated last week
- ☆35Apr 20, 2021Updated 5 years ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 4 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆39May 4, 2024Updated 2 years ago
- Simulator code of the paper "Dissecting and Modeling the Architecture of Modern GPU Cores"☆113Oct 15, 2025Updated last year
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆17Sep 27, 2022Updated 4 years ago