☆13Jun 9, 2022Updated 4 years ago
Alternatives and similar repositories for rvcorep
Users that are interested in rvcorep are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- VexRiscv reference platforms for the pqriscv project☆16Mar 9, 2024Updated 2 years ago
- OpenRule1umPDKを各種環境にセットアップするためのスクリプトです。☆14Nov 13, 2025Updated 11 months ago
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆17Nov 19, 2019Updated 6 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆11Jun 29, 2021Updated 5 years ago
- ☆14Mar 20, 2025Updated last year
- A simple AXI4 DMA unit written in SpinalHDL.☆18Apr 18, 2020Updated 6 years ago
- Wishbone <-> AXI converters☆13Jun 1, 2015Updated 11 years ago
- This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.☆18Jan 31, 2024Updated 2 years ago
- A programming language for FPGAs.☆19May 5, 2018Updated 8 years ago
- ☆19Aug 27, 2022Updated 4 years ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- Simple library for decoding RISC-V instructions☆23Jun 21, 2026Updated 4 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Repo that shows how to use the VexRiscv with OpenOCD and semihosting.☆26Feb 21, 2022Updated 4 years ago
- A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. …☆11May 4, 2022Updated 4 years ago
- ☆11Nov 17, 2025Updated 11 months ago
- System-on-chip design for NOP in NSCSCC 2023.☆15Aug 21, 2023Updated 3 years ago
- ☆14Dec 9, 2025Updated 10 months ago
- CERN PyTorch Tutorial for Jet Images generation with GANs☆10Apr 11, 2018Updated 8 years ago
- ☆16Sep 17, 2026Updated last month
- OpenSoC Fabric - A Network-On-Chip Generator☆18Jun 12, 2017Updated 9 years ago
- CoMeT is a new low-cost RowHammer mitigation that uses Count-Min Sketch-based aggressor row tracking, as described in our HPCA'24 paper h…☆12Jan 23, 2026Updated 9 months ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Pipelined RISC-V RV32I Core in Verilog☆43Apr 9, 2023Updated 3 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆29Nov 21, 2019Updated 6 years ago
- Craft 2 top-level repository☆14May 15, 2019Updated 7 years ago
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 12 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆25Feb 1, 2020Updated 6 years ago
- (Machine) Learning to Do More with Less☆14Jun 11, 2018Updated 8 years ago
- 32-bit Wallace and Dadda Tree Multiplier☆14Jun 26, 2020Updated 6 years ago
- This is a SystemVerilog HDL implementation of Karatsuba multiplier.☆11Jul 8, 2020Updated 6 years ago
- ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface☆18Dec 23, 2020Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Useful utilities for BAR projects☆31Jan 3, 2024Updated 2 years ago
- pyslang-mcp is a read-only Model Context Protocol server for compiler-backed Verilog and SystemVerilog analysis. It uses pyslang to parse…☆21Jun 14, 2026Updated 4 months ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆85Dec 1, 2022Updated 3 years ago
- RISC-V RV32IMAFC Core for MCU☆47May 20, 2026Updated 5 months ago
- Encodes and decodes CWT, EAT and similar format tokens. It supports COSE format signing and verification as well as the UCCS unsigned for…☆11Jul 23, 2022Updated 4 years ago
- Icestudio examples - Community contributions☆18Jan 27, 2019Updated 7 years ago
- oneAPI Deep Neural Network Library (oneDNN)☆10Feb 2, 2022Updated 4 years ago