Alternatives and similar repositories for lowrisc-nexys4

Users that are interested in lowrisc-nexys4 are comparing it to the libraries listed below

• ucam-comparch / clarvi
  Clarvi simple RISC-V processor for teaching
  ☆58Updated 8 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆110Updated 2 years ago
• ucb-bar / sha3
  ☆80Updated last year
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 5 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆42Updated last year
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• rajshadow / 4-way-set-associative-cache-verilog
  Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
  ☆41Updated 8 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• esperantotech / boom-template
  A template for building new projects/platforms using the BOOM core.
  ☆24Updated 6 years ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆57Updated last year
• chipsalliance / uvm-verilator
  ☆97Updated 2 years ago
• riscv / riscv-test-env
  ☆50Updated 4 months ago
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆52Updated 5 years ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆67Updated 6 years ago
• oprecomp / DDR4_controller
  ☆64Updated 4 years ago
• yaozhaosh / chisel-aes
  Chisel implementation of AES
  ☆23Updated 5 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆76Updated last week
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆83Updated 4 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆137Updated 2 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 6 years ago
• verilator / example-systemverilog
  ☆40Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆187Updated last year
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆59Updated 2 years ago
• AmeerAbdelhadi / Multiported-RAM
  Modular Multi-ported SRAM-based Memory
  ☆31Updated 10 months ago
• lingscale / cc01
  ☆31Updated 6 months ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆46Updated 3 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 7 months ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆76Updated 9 years ago