jkorinth / chisel-packagingLinks
IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.
☆11Updated 6 years ago
Alternatives and similar repositories for chisel-packaging
Users that are interested in chisel-packaging are comparing it to the libraries listed below
Sorting:
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- Python/Simulator integration using procedure calls☆10Updated 5 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- Advanced Debug Interface☆15Updated 5 months ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 9 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- A header only C++11 library for functional coverage☆36Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- Cross EDA Abstraction and Automation☆39Updated this week
- SoCRocket - Core Repository☆37Updated 8 years ago
- ☆22Updated 8 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆46Updated 2 weeks ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- ☆31Updated last year
- A Vivado HLS Command Line Helper Tool☆36Updated 3 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- Constrained random stimuli generation for C++ and SystemC☆52Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆71Updated 10 months ago
- ☆12Updated 2 years ago
- Chisel Things for OFDM☆32Updated 5 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- ☆14Updated 5 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- hardware library for hwt (= ipcore repo)☆40Updated 3 weeks ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago
- Provides automation scripts for building BFMs☆16Updated 2 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 9 months ago