Alternatives and similar repositories for riscv-ovpsim:

Users that are interested in riscv-ovpsim are comparing it to the libraries listed below

• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆93Updated 3 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆147Updated 2 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆103Updated this week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆69Updated this week
• riscv-ovpsim / imperas-riscv-tests
  ☆168Updated last year
• riscv / riscv-CMOs
  ☆84Updated 2 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 9 months ago
• ucb-bar / testchipip
  ☆82Updated last week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 8 months ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆78Updated 4 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆221Updated 3 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated last week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆154Updated 4 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆111Updated 2 years ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆219Updated last year
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆64Updated 7 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆166Updated 6 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆142Updated 3 months ago
• sifive / block-inclusivecache-sifive
  ☆77Updated 2 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆84Updated this week
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆34Updated 3 years ago
• riscv / riscv-bfloat16
  ☆33Updated 7 months ago
• riscv / riscv-test-env
  ☆45Updated last month
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆99Updated last year
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆139Updated 2 weeks ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆90Updated this week
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆60Updated 5 months ago
• riscvarchive / riscv-code-size-reduction
  ☆151Updated 11 months ago
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆79Updated 2 months ago