mupq / pqriscv-vexriscv
VexRiscv reference platforms for the pqriscv project
☆15Updated 11 months ago
Alternatives and similar repositories for pqriscv-vexriscv:
Users that are interested in pqriscv-vexriscv are comparing it to the libraries listed below
- ☆17Updated 2 years ago
- SHA3 (KECCAK)☆16Updated 10 years ago
- ☆9Updated 2 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆34Updated 4 years ago
- Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)☆14Updated 4 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆46Updated last week
- ☆11Updated 3 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 7 months ago
- ☆20Updated 5 years ago
- Custom Coprocessor Interface for VexRiscv☆9Updated 6 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆21Updated 4 months ago
- ☆20Updated 7 months ago
- SCARV: a side-channel hardened RISC-V platform☆18Updated 3 years ago
- Chisel implementation of AES☆23Updated 4 years ago
- Platform Level Interrupt Controller☆36Updated 9 months ago
- AXI Formal Verification IP☆20Updated 3 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆29Updated last year
- FPGA implementation of a physical unclonable function for authentication☆33Updated 7 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 5 years ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆44Updated 3 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 7 months ago
- ☆26Updated 3 years ago
- Docker Development Environment for SpinalHDL