mupq / pqriscv-vexriscvLinks
VexRiscv reference platforms for the pqriscv project
☆16Updated last year
Alternatives and similar repositories for pqriscv-vexriscv
Users that are interested in pqriscv-vexriscv are comparing it to the libraries listed below
Sorting:
- HW Design Collateral for Caliptra RoT IP☆112Updated last week
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- ☆12Updated 4 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆57Updated last month
- ☆17Updated 3 years ago
- Chisel implementation of AES☆23Updated 5 years ago
- A configurable SRAM generator☆54Updated last month
- SCARV: a side-channel hardened RISC-V platform☆22Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- ☆20Updated 5 years ago
- SHA3 (KECCAK)☆18Updated 11 years ago
- ☆10Updated 3 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Updated 6 years ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated 2 weeks ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆47Updated 3 years ago
- ☆80Updated last year
- A simple AXI4 DMA unit written in SpinalHDL.☆17Updated 5 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆89Updated last year
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆61Updated 2 months ago
- SystemVerilog Linter based on pyslang☆31Updated 5 months ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- Advanced Debug Interface☆15Updated 8 months ago
- Chisel Fixed-Point Arithmetic Library☆16Updated 9 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 8 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 3 months ago
- Cross EDA Abstraction and Automation☆39Updated this week