bluecmd / wb-axi

Related projects ⓘ

Alternatives and complementary repositories for wb-axi

• wallento / wb2axi
  Wishbone to ARM AMBA 4 AXI
  ☆13Updated 5 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated 6 months ago
• andrewsil1 / NexysPsram
  AXI PSRAM Controller IP for use with Digilent Nexys 4
  ☆10Updated 2 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆12Updated last year
• freecores / wb_builder
  WISHBONE Builder
  ☆13Updated 8 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆36Updated 6 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• AnttiLukats / HackaZynq
  Open Source ZYNQ Board
  ☆30Updated 9 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 5 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• maikmerten / riscv-tomthumb
  A small RISC-V RV32I core written in VHDL, intended as testbed for my personal VHDL learning
  ☆32Updated 6 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• hgomersall / Veriutils
  Verification Utilities for MyHDL
  ☆17Updated last year
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• ucb-bar / chisel-awl
  ☆13Updated 3 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆36Updated 3 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆44Updated last week
• PulseRain / FP51_fast_core
  PulseRain FP51-1T MCU core
  ☆9Updated 7 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 2 years ago
• Cognoscan / VerilogCogs
  Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.
  ☆20Updated 9 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆18Updated 7 years ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆34Updated 3 years ago
• paulscherrerinstitute / xvcSupport
  ☆17Updated 4 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 5 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆54Updated 7 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆34Updated 7 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆33Updated 5 years ago