bluecmd / wb-axiLinks
Wishbone <-> AXI converters
☆13Updated 10 years ago
Alternatives and similar repositories for wb-axi
Users that are interested in wb-axi are comparing it to the libraries listed below
Sorting:
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- A RISC-V processor☆15Updated 7 years ago
- Wishbone to AXI bridge (VHDL)☆44Updated 6 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago
- PicoRV☆43Updated 5 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- Open Processor Architecture☆26Updated 9 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated 3 weeks ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Docker Development Environment for SpinalHDL☆20Updated last year
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- Open Source ZYNQ Board☆31Updated 10 years ago
- WISHBONE Builder☆15Updated 9 years ago
- Collection of hardware description languages writings and code snippets☆28Updated 10 years ago
- ☆30Updated 8 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- Wishbone controlled I2C controllers☆56Updated last year
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- USB 1.1 Device IP Core☆21Updated 8 years ago
- USB Full Speed PHY☆48Updated 5 years ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Updated 10 years ago
- SPI core☆14Updated 6 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- Wishbone interconnect utilities☆44Updated 3 weeks ago
- Next-Generation FPGA Place-and-Route☆10Updated 7 years ago
- Spen's Official OpenOCD Mirror☆51Updated 10 months ago
- Example of how to use UVM with Verilator☆31Updated last month
- A single-wire bi-directional chip-to-chip interface for FPGAs☆125Updated 9 years ago