ucb-ucie / ucieanalogLinks
An open-source UCIe implementation developed at UC Berkeley.
☆15Updated 11 months ago
Alternatives and similar repositories for ucieanalog
Users that are interested in ucieanalog are comparing it to the libraries listed below
Sorting:
- Pure digital components of a UCIe controller☆63Updated last week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated this week
- CVA6 SDK containing RISC-V tools and Buildroot☆66Updated last year
- A libgloss replacement for RISC-V that supports HTIF☆38Updated last year
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆95Updated 2 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- AIA IP compliant with the RISC-V AIA spec☆42Updated 5 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆55Updated 2 months ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆47Updated 4 years ago
- ☆33Updated 3 months ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 11 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆33Updated last year
- Advanced Architecture Labs with CVA6☆62Updated last year
- Platform Level Interrupt Controller☆41Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 8 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- ☆42Updated 3 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆61Updated 5 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆84Updated last week
- Project repo for the POSH on-chip network generator☆46Updated 3 months ago
- PCI Express controller model☆57Updated 2 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆62Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆105Updated last year
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago