《关于浮点运算：作为程序员都应该了解什么？》
☆27Apr 17, 2018Updated 7 years ago
Alternatives and similar repositories for floating-point-guide
Users that are interested in floating-point-guide are comparing it to the libraries listed below
Sorting:
- ☆12Feb 15, 2024Updated 2 years ago
- An instruction of how to modify bios image to enable avx512 for alderlake CPU on modern gigabyte motherboards☆13Feb 2, 2023Updated 3 years ago
- hdmi-ts Project☆13Jun 11, 2017Updated 8 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- ☆38Jul 9, 2024Updated last year
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 6 years ago
- Wishbone <-> AXI converters☆13Jun 1, 2015Updated 10 years ago
- P4FPGA is located at github.com/hanw/p4fpga☆13Jan 27, 2017Updated 9 years ago
- The Duplex trait: interactive streams☆19Sep 6, 2024Updated last year
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 10 years ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆18Updated this week
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- 使用micropython和esp32芯片驱动传感器的学习，适合儿童学习python编程☆16Jan 29, 2019Updated 7 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 6 months ago
- WISHBONE DMA/Bridge IP Core☆18Jul 17, 2014Updated 11 years ago
- FPGA demo for Digilent NEXYS 4 board☆22Oct 2, 2019Updated 6 years ago
- A collection of notes related to RISC-V before they are processed and digested☆18Dec 19, 2017Updated 8 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆26Sep 9, 2025Updated 5 months ago
- On top of SemanticUI, this Scala.js project provides components defined in Ant Design with Binding.scala☆15Jan 1, 2019Updated 7 years ago
- ☆87Jan 30, 2026Updated last month
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆34Oct 23, 2025Updated 4 months ago
- Open-source non-blocking L2 cache☆54Updated this week
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Jul 14, 2020Updated 5 years ago
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago
- A Project for people to study android svc.☆25Aug 12, 2022Updated 3 years ago
- ☆25Dec 5, 2024Updated last year
- ☆11May 31, 2016Updated 9 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆62Jun 27, 2025Updated 8 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 6 years ago
- Contains commonly used UVM components (agents, environments and tests).☆32Aug 17, 2018Updated 7 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Jul 12, 2024Updated last year
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 3 months ago
- ☆31Jun 15, 2022Updated 3 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Sep 17, 2025Updated 5 months ago
- 平头哥玄铁C910的LLVM工具链支持，由PLCT实验室提供，非官方版本☆76Mar 15, 2021Updated 4 years ago
- Wrapper for Rocket-Chip on FPGAs☆137Oct 5, 2022Updated 3 years ago