cnrv / floating-point-guideLinks
《关于浮点运算:作为程序员都应该了解什么?》
☆27Updated 7 years ago
Alternatives and similar repositories for floating-point-guide
Users that are interested in floating-point-guide are comparing it to the libraries listed below
Sorting:
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Updated 3 years ago
- Hardware design with Chisel☆35Updated 2 years ago
- Run Rocket Chip on VCU128☆30Updated last month
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Updated 5 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- Wrappers for open source FPU hardware implementations.☆35Updated this week
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- TEE hardware - based on the chipyard repository - hardware to accelerate TEE☆24Updated 2 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- 平头哥玄铁C910的LLVM工具链支持,由PLCT实验室提供,非官方版本☆76Updated 4 years ago
- Learn NVDLA by SOMNIA☆42Updated 5 years ago
- Helper scripts used to clone RISC-V related git repos inside China.☆16Updated 5 years ago
- ⛔ DEPRECATED ⛔ HERO Software Development Kit☆21Updated 3 years ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Updated last year
- A parallel and distributed simulator for thousand-core chips☆26Updated 7 years ago
- A collection of notes related to RISC-V before they are processed and digested☆18Updated 7 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆59Updated 2 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆30Updated 5 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Updated 9 months ago
- A Simple As Possible RISCV-32I core with debug module.☆42Updated 5 years ago
- RISC-V GPGPU☆35Updated 5 years ago
- Open-source high-performance non-blocking cache☆91Updated 3 weeks ago
- 记录阅读各类paper的想法笔记(关注体系结构,机器学 习系统,深度学习,计算机视觉)☆25Updated 6 years ago
- Open-Source EDA workshop for RISC-V community☆12Updated 3 years ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆20Updated 3 years ago
- HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…☆21Updated 9 years ago
- ☆39Updated 3 weeks ago
- ☆21Updated 4 years ago
- PLCT实验室的 RISC-V V Spec 实现,基于llvm/llvm-project,rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8☆161Updated 2 months ago
- ☆26Updated 8 years ago