YanB25 / TomasuloLinks
An out-of-order execution algorithm for pipeline CPU, implemented by verilog
☆40Updated 7 years ago
Alternatives and similar repositories for Tomasulo
Users that are interested in Tomasulo are comparing it to the libraries listed below
Sorting:
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 3 years ago
- ☆22Updated 2 years ago
- CQU Dual Issue Machine☆35Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆49Updated last year
- Advanced Architecture Labs with CVA6☆65Updated last year
- ☆18Updated 2 years ago
- Pick your favorite language to verify your chip.☆63Updated this week
- A Study of the SiFive Inclusive L2 Cache☆65Updated last year
- ☆86Updated 3 months ago
- ☆36Updated 6 years ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆14Updated 2 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆83Updated last year
- ☆77Updated 3 months ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆65Updated 3 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 9 months ago
- An almost empty chisel project as a starting point for hardware design☆32Updated 6 months ago
- ☆96Updated this week
- ☆67Updated 6 months ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated 11 months ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated 2 years ago
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- ☆24Updated last week
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆29Updated 5 years ago
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆18Updated 6 years ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆27Updated 2 weeks ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- Modern co-simulation framework for RISC-V CPUs☆147Updated this week