An out-of-order execution algorithm for pipeline CPU, implemented by verilog
☆41Mar 27, 2018Updated 7 years ago
Alternatives and similar repositories for Tomasulo
Users that are interested in Tomasulo are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 10 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA wi…☆16Jan 4, 2020Updated 6 years ago
- RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆54Apr 11, 2020Updated 5 years ago
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆10Apr 29, 2024Updated last year
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Nov 28, 2019Updated 6 years ago
- Vector processor for RISC-V vector ISA☆140Oct 19, 2020Updated 5 years ago
- ☆22Nov 3, 2025Updated 4 months ago
- A simple superscalar out-of-order RISC-V microprocessor☆239Feb 24, 2025Updated last year
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- Build edk2 development and debugging environment under win10, for recording some notes and writing self tools.☆13Aug 14, 2022Updated 3 years ago
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Mar 15, 2026Updated last week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Dec 19, 2021Updated 4 years ago
- ☆27Jun 12, 2022Updated 3 years ago
- 无需配置特定环境，在 Docker 容器环境中编译 linux-2.6.26，并在宿主机的 qemu 中运行☆13Jul 16, 2024Updated last year
- ☆16Apr 21, 2019Updated 6 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Tracker for books I've read. Looking for suggestion and inspirational for others. :)☆11Feb 11, 2026Updated last month
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- RISC-V IOMMU in verilog☆23Jun 18, 2022Updated 3 years ago
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 4 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- ☆16Mar 18, 2025Updated last year
- HW JPEG decoder wrapper with AXI-4 DMA☆37Oct 25, 2020Updated 5 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.☆15Jan 14, 2022Updated 4 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- gem5 相关中文笔记☆17Dec 2, 2021Updated 4 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Apr 7, 2025Updated 11 months ago
- ☆14May 15, 2023Updated 2 years ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- Tracing JIT compiler and runtime for a subset of the JVM☆26Jan 1, 2024Updated 2 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆14Mar 12, 2026Updated last week
- NUDT 高级计算机网络实验：基于UDP的可靠传输☆18Jan 8, 2024Updated 2 years ago
- PA + Labs for Operating Systems 2019 course in NJU taught by JYY.☆12Aug 6, 2019Updated 6 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆184May 8, 2025Updated 10 months ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago